programmablelogicZONE Feed http://www.en-genius.net This feed provides access to the latest information provided on the programmablelogicZONE. en-us editor@en-genius.net webmaster@en-genius.net IMS RSS FEED GENERATOR pl_news_050508_4 Northwest Logic announces a complete PCI Express 2.0 solution for Xilinx Virtex-5FXT devices.  http://www.nwlogic.com/news/news/Virtex5FXT_NWL_HiTech.pdf Mon, 05 May 2008 00:00:00 GMT engeniusfeeditemid-5 pl_news_050508_3 JESD204 serial ADC standard now supported by Lattice SerDes-equipped ECPM2 low-cost FPGAs. http://www.latticesemi.com/corporate/newscenter/productnews/2008/r080415ecp2mfpgassupporth.cfm Mon, 05 May 2008 00:00:00 GMT engeniusfeeditemid-3 pl_news_050508_2 National Instruments integrates Xilinx Virtex-5 FPGA technology into new customizable I/O devices. http://digital.ni.com/worldwide/bwcontent.nsf/web/all/2F1CAE72BFBEE17C8625741A006E1D0C Mon, 05 May 2008 00:00:00 GMT engeniusfeeditemid-4 pl_news_050508_1 Lattice ultra-low-power CPLD family addresses high volume portable applications. http://www.latticesemi.com/corporate/newscenter/productnews/2008/r080428announcesnewcpldfa.cfm Mon, 05 May 2008 00:00:00 GMT engeniusfeeditemid-6 pl_app_021808 Build a triple speed Ethernet data path reference design with Altera’s Stratix II GX FPGAs. http://www.altera.com/literature/an/an483.pdf Mon, 18 Feb 2008 00:00:00 GMT engeniusfeeditemid-7 Lattice And Aldec Form Alliance For FPGA Design And Design Verification Lattice Active-HDL Lattice Edition Mixed-Language Design Support http://www.en-genius.net/site/zones/programmablelogicZONE/product_reviews/plp_050508 Mon, 05 May 2008 00:00:00 GMT engeniusfeeditemid-1 Hot Dogs, Flybys and Goodbyes Lee Goldberg bids goodbye to the shabby, funky airport that is home to some of his dearest flying memories. http://www.en-genius.net/site/zones/programmablelogicZONE/editorial_opinion/pled_041408 Mon, 14 Apr 2008 00:00:00 GMT engeniusfeeditemid-0 Fast, Flexible FPGA/FPGA Processor Memory Configuration If serial Flash is taking too long to configure your large FPGAs, here’s a low-cost, PLD-based strategy for accelerating code loads in your next design. http://www.en-genius.net/site/zones/programmablelogicZONE/technical_notes/plt_040708 Mon, 07 Apr 2008 00:00:00 GMT engeniusfeeditemid-2