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acquisitionZONE Products for the week of April 21, 2008
Linear Technology Says…
LTC2274: 16-bit, 105 Msample/s Serial Output ADC Conserves FPGA I/O Pins
Linear Technology Corporation announced a 16-bit, 105Msps ADC that establishes a simple, new benchmark for digital communication between high speed ADCs and FPGAs. The LTC2274’s new high speed 2-wire serial interface greatly reduces the number of data input/output (I/O) lines required between a 16-bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single, self-clocking, differential pair communicating at 2.1Gbps, freeing up valuable FPGA pins.
Serial data communications offers simplified layout, and requires less board area for routing, while providing the flexibility to route across analog and digital boundaries. In noise sensitive applications, the serial interface provides an effective isolation barrier between digital and analog circuitry and serves to eliminate coupling between the digital outputs and analog inputs to reduce digital feedback.
The LTC2274 output data is serialized according to the JEDEC serial interface specification for data converters (JESD204) using 8b10b encoding, and is compatible with many FPGA high speed interfaces including Xilinx’s Rocket IO, Altera’s Stratix II GX I/O and Lattice’s ECP2M I/O. At 2.1Gbps, the LTC2274 offers the fastest high speed serial interface of any ADC on the market today. Applications such as leading edge communications equipment, multi-channel systems, space-constrained designs, and instrumentation all benefit from the LTC2274’s unique interface and feature set.
EN-Genius Says…
This part is clearly based on the 105 Msample/s 16 bit LTC2217 with the biggest major difference being, of course, the serial (instead of parallel) output. The change reduces the pin count of the package from 64 to 40 and there would, naturally, be a similar pin count on the receive side of the serial signal which is the whole purpose of the part: to reduce the number of I/O pins on an FPGA, or ASIC, needed to be dedicated to the digital input signal.
The power consumption of the LTC2274 is higher than the LTC2217, up from 1.19 W to 1.3 W, and the noise floor has fallen from 81.3 dB to 77.7 dB. Those should not be of concern on a well-designed PCB and the exposed pad on the bottom of the part must, of course be soldered down for heat dissipation. The new part takes all the A to D tricks used in the LTC2217 and still offers a full power bandwidth of 700 MHz.
The converter part of the device uses a 3.3 V rail while the serializer can be run from 1.2 V to 3.3 V. The encoder on the Linear part needs to be synced from the ASIC or FPGA.
The use of serial to drive an FPGA or ASIC makes a lot of sense. But it is a double-edged sword because the designer has to deal with a high-frequency problem that he might not have been exposed to before. I don’t know the history of the JEDEC JESD204 standard –except for the fact it was ratified in April 2006 – and it’s a little surprising that it is JEDEC and not the IEEE who took it on, but it is not written that tightly. (Please observe protocol, and the law, by not making multiple copies of the standard without a license from JEDEC.)
The standard is for serial connection of converters to other devices with rates between 312.5 Mbit/s and 3.125 Gbit/s (with the 8b/10b encoding being used the output of the LTC2274 will max out at 2.1 Gbit/s). It is for unidirectional transmission over a maximum path of 60 cm (on FR-4) including one controlled connector. The standard is CML-like, dc balanced, and directly-coupled outputs are to be preferred, hopefully using the same rail for the receiver as for the serializer on-chip.
The first applications are most likely to be test pieces from the FPGA and ASIC vendors before the developers really get into it. I know suitable receivers have already been developed by Lattice and Xilinx. If this takes off as a workable system – and there is little reason to see why it should not – then the volumes will become huge and demand will spill over into other systems.
Apart from the 105 Msample/s part (which can be run down to the limit of the PLL system of 20 Msample/s) there will be two other pin-compatible family members with the 80 Msample/s LTC2273 and the 65 Msample/s LTC2272. The LTC2274 is priced at the same level as its LTC2217 cousin.
The LTC2274 is sampling now and demo boards are available. The part will be in production in July 2008 in thermally-enhanced QFN-40 priced at $68 in 1000-piece lots.
Data Sheet
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