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And The Winner Is…
by Lee H Goldberg
It was lots of fun helping organize Vitesse’s VScope Design Challenge contest (Introduced here in connectivityZONE this February), but the real work began when we took our last entry a couple of weeks ago and the process of picking a winner began. Selecting a grand champion between the two finalists was tough because both entries embodied very innovative and practical ideas that went well beyond any application that Vitesse had originally intended for their chips.
In the end, the judging team awarded first place to the entry titled Circuit and Algorithm for using VScope to Identify the Sources of Crosstalk and Noise Coupling Induced Jitter in Data Communication Systems, written by Dr. Cosmin Iorga, founder and president of NoiseCoupling.com. The paper describes an innovative method for identifying the sources of deterministic jitter in data communication systems.
Second place honors were awarded to Mr. Fadi Daou, CEO of MultiLane SAL, who submitted an entry entitled XFP Module with VScope Capability. In his paper, Mr Daou describes how a VScope chip can be embedded in an XFP module, giving it the ability to perform optical channel monitoring and provide feedback on the quality of the received optical signal. By sampling the signal within the module, equipment manufacturers can help their customers perform channel optimization and comprehensive signal analysis without an entire rack of expensive test equipment.
The technical innovation evident in both entries made choosing the first prize winner a difficult task, but it became even more difficult as we realized that the XFP module application has significantly more commercial potential in high-volume applications. In fact, I would not be surprised to see a slightly-polished version of Mr. Daou’s entry being published by Vitesse as a reference design as it has the potential to sell LOTS of chips.
Despite this, the team finally chose Dr. Iorga’s Circuit and Algorithm entry as the 1st place winner based on several factors:
- Using your chip to tease out secondary and tertiary noise and jitter sources is a truly innovative, and potentially extremely useful application. It could give some direct visibility into certain classes of problems that are usually explored indirectly or through mathematical models
- While both entries were well-documented, Dr Iorga put an enormous amount of work into detailing the application and supplying the governing equations used to extract the individual noise sources from the overall signal.
- Finally, I believe this technique has some serious commercial applications, albeit in lower volumes than the XFP module application that took 2nd prize. I even suspect that there may even be the basis of a versatile, and commercially-viable, piece of test equipment lurking inside this paper.
Thanks again to Richard Interrante, Michelle Lozada; and Juan Garza at Vitesse, and our own team here at EN-Genius for all the heavy lifting they did behind the scenes to make the Design Challenge a big success and, more important, lots of fun.
Comments? Questions? Suggestions for a new design contest? Write me at lhg at en-genius dot net – or post your comments on our blog!
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