connectivityZONE Products for the week of February 4, 2008

Vitesse Semiconductor Says…

Latest-Generation Signal Integrity Solution for Backplane Design and Communications Systems
Integrated VScope waveform viewing technology answers the call for improved signal integrity analysis and remote monitoring of live signals

Vitesse Semiconductor Corporation has announced the VSC3406, a 6.375 Gbits/s multi-rate backplane transceiver. The VSC3406 builds upon Vitesse’s portfolio of proven, industry-recognized technology, incorporating the latest clock-data recovery (CDR) techniques and signal integrity toolset for backplane and interconnect design.

The VSC3406 is the first in a family of CDRs to feature Vitesse’s new VScope waveform viewing technology that embeds an oscilloscope function into the receiver of input CDR circuits. This comprehensive signal integrity solution gives engineers a single device that enables both a high speed transceiver function and verification mechanism.

"Embedded oscilloscope functionality can potentially lower network testing and maintenance costs, an ongoing concern for anyone who manages a network", said Aileen Arcilla, senior analyst - semiconductors: networking, broadband and storage for International Data Corporation (IDC). "Providing this means of remote diagnostic capability can offer telecom carriers and data center managers a more direct way to verify signal integrity within the data path itself and take corrective action in a more timely manner."

As the most complete 6 Gbits/s backplane signal integrity solution available to date, the VSC3406 6.375 Gbits/s multi-rate, multi-function backplane transceiver has six high-speed differential transmit and receive interfaces, complete with on-chip termination ideal for interfacing to a variety of media such as PCB traces, cables or optoelectronic devices connected to optical fiber.

The VSC3406 features unique rate multiplication modes that allow bandwidth doubling or quadrupling over existing interconnects. Boasting a 2-to-1 rate multiplier mode that allows data "multiplication" up to 6.375Gbits/s, the VSC3406 can be used to double bandwidth over existing backplanes. A typical application includes XAUI rate-doubling for efficient transmission in high-speed backplanes over half the number of wires. Coupled with the signal equalization function, these rate multiplier modes can be used to run double and quadruple the amount of bandwidth over existing copper traces. This gives customers the ability to field-upgrade equipment to handle greater bandwidth by upgrading line cards and switch cards in existing equipment.

With a single reference clock input, the VSC3406 achieves highly advanced operations at any data rate between 0.125 Gbits/s and 6.375 Gbits/s. The multi-rate CDR of the VSC3406 makes it ideally suited for next-generation backplanes and communication equipment running a variety of protocols, including Gigabet Ethernet, XAUI, Fibre Channel, Serial Attached SCSI (SAS), Serial ATA (SATA) and PCIe. A fully non-blocking, multicast architecture allows the VSC3406 to be user-configured via a simple, two-wire serial interface for a broad range of signal conditioner, retimer, crossbar, or rate multiplication applications. A high degree of signal integrity is achieved by means of configurable input and output equalization. Cost-effectiveness is realized because engineers can use one product across multiple applications and platforms allowing for maximum re-use and R&D savings.

The per-channel clock and data recovery enables protocol retiming and addresses both random and deterministic jitter, eliminating data degradation for Carrier Class system-level performance. As well, the VSC3406 works from a single reference clock with per-channel clock dividers, enabling multi-speed lanes and protocols in OEM systems.

VScope Waveform Viewing Technology

VScope embedded waveform viewing technology is a per-pin "micro-oscilloscope" that enables new diagnostic capabilities during system development, delivering the ability to perform remote monitoring of live signals on deployed systems. Vitesse’s patented VScope technology addresses the accessibility and accuracy challenges often faced by engineers brought about by advancements in integrated equalization technologies. VScope presents system designers with new dynamics and economics in backplane design, signal integrity analysis and remote monitoring of communication systems.

EN-Genius Says…

The Vitesse VSC3406 6.5 Gbit/s multi-rate backplane transceiver adds a couple of important new features to the solid SerDes products they’ve been kicking out for some time now. Besides its higher speed capability, the transceiver has a clever on-chip sampling circuit that gives you a receiver’s eye view of an otherwise impossible-to-see signal. While this is not the first product to offer a so-called "Chip Scope function," the well-engineered software that accompanies it gives you a much better idea of what’s actually going on in your cable, backplane, or PCB trace than I’ve seen before. Between the transceiver’s ability to open up a tightly-closed eye pattern, its crossbar switch/retimer capabilities, and the clever package of support software that will help you fine tune it, this Vitesse solution should go a long way towards making 5G designs less painful to implement.

The VSC3406 functionality is relatively straightforward, having evolved from several earlier generations of SerDes transceivers and retimers. Configurable to support either protocol retiming or transparent operation, it can provide either straight buffering, or channel aggregation for 2 lanes or 4 lanes. This multiplexing function enables it to serve as a rate doubler. This comes in very handy when you are trying to get slower legacy cards and devices to operate on higher-speed backplanes. It also supports a 1G to 4G rate quadrupling mode.

Vitesse employs an equalization scheme that combines a configurable (fixed-slope) analog equalizer from earlier designs with a new FIR filter to provide the extra signal processing needed to pull a clean signal out of a less-than-ideal channel at 6 Gbit/s. A relatively conventional programmable pre/de-emphasis circuit is employed on the transmit side. While it does not employ the adaptive (DFE/FFE) techniques I’d have expected to see at this speed plateau, it seems to work quite well and strikes a good balance between power, cost and performance.

Then there’s the V-Scope feature that Vitesse likes to refer to as an oscilloscope-on-a-chip. It’s not exactly an oscilloscope but a clever set of on-chip slicer circuits that provide a digitized version of the waveform identify the data eye error-free region, and its optimal sampling point. Software provided with the VSC3406 allows you to process the data it provides into a traditional eye diagram, which also incorporates color coding to indicate the percentage of time that a signal spends in a particular amplitude/phase position.

By allowing you to see precisely what the chip’s CDR sees, the VSC3406 eliminates most of the guesswork involved with debugging high-speed link designs during development. The same capabilities can be used as the basis for a powerful diagnostic tool that enables non-intrusive remote monitoring and analysis in operational equipment. An on-chip PRBS generator can be used to provide a known-good signal for loop-back or end-to-end testing.

While there have been several products (Accelerant and Quake come to mind) that provided this basic chip-on-scope capability, Vitesse has gone much further by incorporating a novel BER measurement circuit. It uses the signal from the first locked CDR to generate a second relative timing signal that the oscilloscope can be adjusted to inspect the signal at any point in time.

A comparator checks to see if the recovered data at a given point in the signal matches the actual recovered data to provide a real-time BER at any point along the waveform.

This second circuit allows you to build up tables that record the number of bit-by-bit mismatches per unit time (BER) for each location in time and amplitude across the waveform that can be processed by Vitesse analytic software to provide much more information than a traditional eye diagram.

Among other things, the software can present a color-coded picture of the eye which identifies regions of a particular error level. It can also produce something that resembles a 3-D version of a standard Bathtub Plot.

It’s difficult to tell from a 90-minute briefing just how good any software package actually is but, from what I saw, it does appear that Vitesse has at least the foundations of a tool that will let you really understand much more about their device and the environment it’s functioning in. With all that data collection capability, it would be great if Vitesse developed a LabView module that would allow any other LabView-enabled instrument to configure the VSC3406 and collect data from it. When I asked Vitesse about this, they said that several customers have already requested similar capabilities and that they are busy trying to either locate the internal resources to create a set of LabView utilities or find a 3rd-party interested in developing the package as a product. Once this is done, I would also love to see Vitesse provide drivers that allow their chip to work with other third-party software, such as spreadsheets, statistics analysis, and advanced visualization packages.

General samples of VSC3406 devices will be available in the second quarter of 2008 in FCBGA-81. The VSC3406 will be priced at $60 in.

Editor's Note: There have been several other products that offer some sort of visibility into what the receiver sees, including several of Quake Technologies (recently acquired by AMCC) 10GbE transceivers (see our July 2006 review), and most of the SerDes backplane transceivers that used to be manufactured by Accelerant before they were acquired by Synopsys and moved from selling chips to IP cores. Accelerant IP still lives on in the SerDes interfaces used in some of Agere’s (acquired by LSI Corp. in 2007) more advanced networking and storage products (discussed in a Dec 2004 review).
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