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connectivityZONE Products for the week of February 6, 2006
Synopsys Says…
Seeing Is Believing: Synopsys SerDes Cores for PCIe, SRIO, XAUI and SATA Deliver on Promises for Reach, Margin, & Power
Synopsys, Inc. has expanded its DesignWare Mixed-Signal intellectual property (MSIP) portfolio with new ultra low-power PCI Express, XAUI and SATA physical layers (PHYs) in the 130- and 90-nanometer (nm) processes. These high-performance, mixed-signal PHYs offer highly differentiated, advanced built-in diagnostics for evaluating link performance and margin. When combined with the DesignWare digital controller cores and verification IP for PCIe and SATA protocols, the new PHY IP provides an optimized, lower risk, single vendor solution for designers incorporating these protocols in their system-on-chips (SoCs).
The new PHYs provide numerous benefits to the SoC designer, including compliance to the relevant standards specifications, the industry's smallest cores, low jitter and high receive sensitivity, resulting in a lower system bit error rate (BER) and a robust design with maximum margin and minimum power. The new solutions allow designers to significantly reduce power, requiring only 30 to 50 percent of the power consumption per lane of present solutions. These PHYs are based on an advanced analog architecture designed to scale to the next generation of data rates and process technologies as new high-speed SERDES protocols evolve.
Today design engineers developing SoCs for networking, storage, computing and consumer applications use PCIe, SATA and XAUI PHY's for high-speed interconnects operating at speeds from 1.25 gigabits per second (Gbits/s) to 3.125 Gbits/s. Testing links at these speeds, however, Synopsys' new PHYs incorporate advanced, built-in diagnostics - accessible through JTAG (Joint Test Action Group) - that are designed to replace traditional external loopback pass-fail testing with testing the link margin at speed. This approach is far superior because it allows designers to measure the eye-opening directly and verify the integrity of the signal, channel, and receiver while using only a conventional low-speed digital tester. This advanced approach reduces the total cost of ownership of the PHYs by providing excellent test coverage of the analog nature of high speed PHY's without using sophisticated high-cost test equipment. Support for Automated Test Equipment (ATE) is provided by delivering simple pass-fail JTAG vectors that ensure maximum test coverage when the PHYs are tested in production without the need for developing a complex test program.
"With the addition of the new PCIe, SATA and XAUI PHYs to its IP portfolio, Synopsys clearly demonstrates its commitment to delivering low-power, high-performance interconnects," said Jag Bolaria Senior Analyst at The Linley Group. "These new PHYs are very low in power consumption and include advanced features such on-board diagnostics and ATE."
"The release of the new PHYs firmly establishes our leadership in Mixed-Signal IP and in complete solutions for PCIe, SATA and XAUI. We are now targeting the next generation of high-speed, high-performance serial interconnects," said Guri Stark, vice president of Marketing, Synopsys' Solutions Group.
EN-Genius Says . . .
One of the challenges of writing about cutting edge chips is that you often have to evaluate them without ever seeing them operate, and often before there's a single piece of working silicon. That's why I jumped at the opportunity when Synopsys offered to demonstrate actual examples of the high-speed SATA/XAUI/PCIe IP cores initially announced in September, 2005. Back then they made some serious claims for these "one-core-fits-all" devices which use a single mixed-signal PHY and a series of digital personality elements to create SerDes elements that support SATA, PCIe, XAUI (with a CX-4 option), and Serial RIO interfaces.
Since many people on the design team that cooked these cores up are refugees from Accelerant (a high-performance backplane transceiver maker acquired by Synopsys a couple of years ago) I was inclined to believe their claims that they'd deliver extremely low power consumption and a compact silicon footprint. It was especially heartening to learn that they'd re-used a lot of Accelerant's on-chip test technology that had proven quite useful in backplane applications. Of course some doubts remained when I wrote the first review since they were very reluctant to share many details behind the SerDes cores' design. Adding to my concerns were the many things that can go wrong when a technology is transplanted to a new company and a new application.
I'm pleased to say that any reservations I might have had were put to rest recently when Synopsys shared some of the details of their design and I got to watch a "semi-live" demonstration of a large test chip that they had put together with the sole purpose of evaluating their SerDes cores. I use the term "semi-live" because I watched it on a web hookup (using WebEx conferencing software) with the actual chip and test setup located on the West Coast, around 2500 miles from my office. Thanks to this really clever software I was able to see both the actual test lash-up and the LabView screens displaying the chip's transmitted signals and the outputs of its receiver as viewed by the integrated sampling scope and BERT circuitry.
But before I go into further details about the demonstration, it's probably useful to pass on some of the details of Synopsys' SerDes core design that they shared with me. One of the juicier tidbits is the secret behind their extremely low power consumption. Rather than do what everyone else has done and try to put their own spin on the commonly-used CML current-mode circuits these designers put on their analog thinking caps and came up with a new approach that uses a Thévenin-based (voltage) source that produces the requisite current by driving a 50-Ω series resistor. Synopsys says that part of the circuit's success is due to an on-chip regulated supply that's controlled by an integrated bandgap reference.
From what I could see on my screen during the demo, this improved drive circuit lives up to Synopsys' claims for drawing about half the power that a standard current mode circuit would (running from a 2.5-V logic supply). Depending on the application and the voltage levels you use in your design, each serial link can draw as little as 45 mW/lane (vs 80 mW - 90 mW for a typical PCIe transceiver) when running at 2.5 Gbit/s. And, even when running at 3.125 Gbit/s for XAUI applications, Synopsys reports typical power levels of 55 mW/channel. Just to keep things honest you should also note that there is an additional 20 mW you must budget in for the clock and overhead circuitry that's shared by each group of one to 16 SerDes channels supporting a particular link.
 Synopsys also revealed a few details of its CDR architecture. It consists of a digitally-controlled PLL which uses both local reference clock, and a second-order timing loop to make it insensitive to run length. This allows it to maintain frequency lock across a 10 k-bit dead spot without any transition and remain stable with up to 5000ppm frequency offset.
And while they did not go into equal depth about their line equalization technology, I did get a better picture of how they rely on a linear transmitter pre-emphasis circuit that delivers 16 levels of signal boost between 0 dB and 5.8 dB to augment the 0.5 dB to 4 dB worth of linear equalization on the receiver. When I asked what had happened to the sophisticated DFE equalizers found on earlier Accelerant circuits, Synopsys explained that it was not necessary for the slower speeds at which these chips run.
Getting back to the demo, the test chip had been fabricated with a single quad-channel SerDes interface 250-k gates worth of logic that had been designed specifically to generate as much noise on the substrate and metal interconnect layers as possible. This included a full PIPE interface and noise generator (an 11-bit LFSR clock tree).
As part of the demonstration, the web-conference software allowed me to use a web cam to see the test bed that was being used this set-up. It supported three different test modes to demonstrate the SerDes operation in three very different environments. The PCI Express demonstration ran the signal though 17 inches of normal FR-4 PCB that you'd find on your average next-gen ITX card or server blade. The SATA demonstration set up involved running a simulated driver signal through 1 m of SATA cabling, a couple of connectors, and a set of "typical" PCB traces. Finally, their XAUI/CX-4 demo ran through 15 m of SMA cabling onto an edge card, and across a Tyco demonstration backplane. The CX-4 test setup included four lanes of 3.125 GHz traffic running in adjacent traces across the Tyco backplane.
I watched signals being run across various length runs and fed into the receiver and out the other side. And thanks to the "Scope-on-Chip" technology (borrowed from Accelerant) that provides both sampling scope and BERT functionality built onto the silicon., I was able to see the receiver's output before it was run through the CDR and converted to a bit stream. The chip feeds outputs from its digital CDR's onboard sampling and slicer circuitry to its JTAG interface. These signals are processed by a garden-variety PC running customized MATLAB software that turns it into a virtual digital oscilloscope. The SerDes core's integrated BERT capability also allowed the "PC-scope" to easily locate the edges of eye diagrams and perform other performance analysis tasks.
The results were impressive, to say the least! I saw the test bed produce "live" signals with significant levels of voltage and phase margin, even under challenging conditions. While I'm sure Synopsys made sure I saw the chip running under close to optimal conditions, they did make sure to vary signal path, signal levels, supply levels and speeds enough to show that the cores worked well at the corners of their specifications. And to keep things at least somewhere close to real-world conditions, they were often running signals on adjacent lines. For example, they had all four lanes running during much of the PCIe demo, something that was evident from small crosstalk-induced changes in the test signal when the adjacent traces became active. While the small amounts of extra "fuzz" in the eye diagram caused by the adjacent signals did not cause any appreciable degradation in performance, they were reassuring evidence that this was really a live demonstration.
Between the performance I got to witness firsthand and the self-diagnosis features these cores pack, it looks like they're good candidates for the PCIe, SATA, or XAUI interfaces in your next design. And some time in May, 2006, you'll also be able to get a version of the core that's Serial RapidIO-certified as well.
Data Sheet
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