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connectivityZONE Products for the week of May 5, 2008
Synopsys Says…
5.0 Gbit/s PCI Express 2.0 PHY IP Provides Designers With Complete, Single-Vendor Solution
Synopsys, Inc. has announced the availability of the DesignWare PHY IP for PCI Express 2.0 (Gen II), based on the PCI Express 2.0 base specification. This product release further extends Synopsys’ IP leadership by providing designers with the IP industry’s only complete, silicon-proven PCI Express 2.0 IP solution, including digital controllers, PHY and verification IP from a single vendor. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 5.0 Gbits/s PCI Express interface into their high performance system-on-chip (SoC) designs.
PCI Express 2.0 doubles the 1.1 specification transfer speed from 2.5 Gbits/s to 5.0 Gbits/s per lane, meeting the demand for both increased bandwidth and narrower interconnect links in data center , storage, high-end graphics and networking infrastructure applications. Backwards compatibility with the PCI Express 1.1 and PIPE specifications, allows designers to optimize performance and power while maintaining interoperability with existing devices. The DesignWare PHY IP substantially exceeds the electrical specification in areas such as jitter, margin and receive sensitivity, thus delivering a robust design without sacrificing performance. The DesignWare PHY IP for PCI Express 2.0 includes advanced built-in diagnostic capabilities and ATE test vectors enabling at-speed production testing of the PHY. It is implemented in standard CMOS digital technologies and does not require special process options, providing both ease of integration into a SoC, and ensuring high production yields.
“We have had a very long term relationship with Synopsys on PHY IP and have always been impressed with the robust architecture, their technical knowledge and expert technical support,” said Joe Abler, manager, IBM Common Platform IP Strategy. “The DesignWare PHY for PCI Express 2.0, which is available in IBM’s 65-nm ASIC and Foundry offerings, enables us to successfully deliver high quality solutions to the market.”
“PCI-SIG welcomes the introduction of the new Synopsys DesignWare PHY IP for PCI Express 2.0,” said Al Yanes, PCI-SIG chairman and president. “As an active member of PCI-SIG, Synopsys helps to prepare the industry for the proliferation of the PCI Express technology and we are happy to see them enable designers to integrate the latest specification into their chips.”
“With the release of the DesignWare PHY for PCI Express 2.0, designers can now get access to a complete silicon-proven IP solution from a single, trusted vendor,” said John Koeter, senior director of marketing for IP and Services at Synopsys. “As the leading provider of PCI Express IP, we continue to invest heavily in our IP roadmap to deliver low risk, high quality IP solutions that help our customers bring differentiated products to the market faster.”
EN-Genius Says…
Although a relatively small fraction of our readers are actively involved with designing ASICs or ASSPs, Synopsys' new PCI Express 2.0 IP is worth noting by anyone expecting to be using this high-speed interconnect technology in the next couple of years. Besides signaling the beginning of PCIe 2.0 arrival in the mainstream market, the IP performance and feature set will set a much higher bar than simple standards compliance for both IP and merchant silicon. The higher level of performance Synopsis claims to provide will become increasingly important as PCIe finds more and more applications as a backplane technology and a box-to-box interconnect standard where channel conditions will be a bit more challenging than the short PCB runs it was originally designed for. Synopsys has also packed in several clever features that are so handy that they may set a new baseline for other IP and ASSPs using PCIe 2.0 interfaces.
Even discounting the extra bells and whistles (we’ll discuss them shortly), the new PHY IP is noteworthy because of the extra care Synopsys put into ensuring that they can cope with the many challenges that a 5 GHz signal encounters in a CMOS chip and in the channel it is coupled to. Synopsys says that the PCIe 2 requirements have much stricter limits on how much jitter a node can tolerate or generate than the original 2.5 Gbit/s PCIe spec. In order to raise the PHY resistance to deterministic jitter (induced mostly by power supply noise and substrate coupling) Synopsys has employed current-oriented cascode elements that eliminate its susceptibility to voltage variations. Random jitter from submicron effects in the PLL/VCO are minimized by up-sizing selected devices enough to make their threshold and drive characteristics more predictable.
The PHY designers also paid attention to the wide range of channel conditions that PCI Express is used in. Besides the standard pre-emphasis required by the PCIe 2.0 standard, they’ve included a register-programmable launch amplitude control that allows a designer or user to kick up the signal to overcome whatever impediments it encounters. Conversely, the amplitude control can be used to trim power consumption if the PHY will be working in a relatively benign, low-loss channel. On the receive side, they’ve provided enhanced sensitivity with an extra stage that adds 2 – 3 dB worth of gain to the signal chain. Having extra sensitivity gives you more margin or longer reach in challenging channel conditions and allows for even lower transmit power in low-noise environments.
To minimize implementation risk, Synopsys made sure the PHY works reliably with their PCIE Gen2 controller IP using a series of 65-nm test wafers to test, characterize and verify compatibility before releasing a commercial product. They also conducted similar tests to make sure that the IP remained within spec limits across a wide range of process variations. It’s interesting to note that Synopsys reports preparations are already underway to move the PHY design to a 40-nm process node with 1.8 V core voltages – no small task for an analog-intensive circuit like this one.
There are also a few other features that add value to these PHYs including an integrated chip-scope function and diagnostic software that enables a digitized real-time eye diagram to be presented via a JTAG interface. Derived from the same clever technology that helped Synopsys 2.5 Gbit/s PCIe PHY win our 2006 Product of the Year Award (reviewed here February 2006), it can give you a receiver’s eye view of the signal that is very helpful during both chip and product development. The new IP also comes with a handy piece of software that loads the chip-scope internal slicers and comparators with Synopsys-supplied test vectors which allow the chip to automatically verify critical performance values without any external ATE. A Synopsys-supplied GUI lets production test engineers plug in parameters to reliably verify threshold, voltage & phase margining, jitter, and transmit level in a few milliseconds. Heck, the savings in ATE costs alone should repay whatever you pay Synopsys for their IP.
Designers working with low-cost wire bond packaging will also appreciate the GDS II compile options that customize the PHY design transceivers to drive either a flip chip or wire bond. Don’t expect miracles here but Synopsys says that the alternate compile option allows it to support 3 – 4 nH worth of bond wire (at the cost of a bit more power and silicon area). While most high-end devices have already migrated to flip chip or BGA packaging, the ability to support the less costly but lower-performing wire bond packages could become important as PCIe 2 matures and enters more cost-sensitive markets.
The Synopsys introduction of their PCI Express 2.0 PHY is very well-timed to support the ASIC and ASSP development efforts that I expect to ramp up towards the end of the year. PCIe 1.0 speed and PCB space savings has helped it become the de facto standard in PCs and enterprise computing within a few of years of its introduction, not to mention its growing popularity in high-performance embedded applications. I’d expect PCI Express 2.0 will enjoy a similar adoption curve in high as need for speed grows and the first compliance tests (scheduled for August of this year [2008)]) give the industry the confidence it needs to commit to a 2x speed-up. Synopsys has added to that confidence by offering a high-performance, low-risk PCIe 2.0 solution that frees up chip makers from the burden of developing a costly chunk of IP that does not directly differentiate their products.
The DesignWare PHY IP for PCI Express 2.0 is in production for 4x and 8x lane applications.
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