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connectivityZONE Products for the week of August 25, 2008
Gennum Corporation Says…
PCI Express Bridge for High Data Rate Embedded Applications
First four-lane PCIe bridge reduces design time by up to 80%
Gennum Corporation has unveiled the industry’s first four-lane PCI Express (PCIe)-to-local bus bridge chip. The highly integrated PCIe bridge offers four lanes at 2.5Gb/s or 10Gb/s in each direction enabling designers of high-speed embedded applications to leverage the full potential of the PCIe standard with a low cost, turnkey solution and speed time to market by up to 80 percent.
A new addition to Gennum’s growing high-performance PCIe portfolio of bridges and repeaters, the GN4124 PCIe bridge offers three to six times the performance over legacy bridge and endpoint products by providing 1600MB/s burst throughput and full duplex operation. This enables such capabilities as supporting multiple channels of uncompressed HD or 1080p video, thus meeting the demands of higher data rate applications in video broadcast, medical, data communications and industrial control markets. The new product is being demonstrated this week at IDF.
“We continue to see increased demand for higher performance PCIe solutions, beyond the traditional PC applications,” said Martin Rofheart, senior vice president and GM, Analog & Mixed-Signal Products, Gennum. “With this four-lane solution, we enable designers to reduce both the cost and power dissipation of their designs, enabling a broader set of high data rate applications to quickly and easily migrate to PCIe. In short, we enable designers to spend time on their design—not spend their time and resources on making PCIe work.”
The integrated functionality of the GN4124, which is bundled with Gennum’s royalty-free local bus field programmable gate array (FPGA) intellectual property (IP), incorporates the PCIe physical layer and digital controller on-chip, thus eliminating the need for this functionality to be integrated into a stand-alone, complex and expensive FPGA. For the designers, this means a feature-laden solution with solution cost savings approaching 50 percent.
The GN4124 is aimed at a variety of PCIe applications in the communications, broadcast video, industrial control, medical and commercial off-the-shelf (COTS) markets. The widespread adoption of PCIe in these markets is driving the need for a low-cost, easy-to implement bridging solution that fully utilizes the performance capabilities of the PCIe standard. While different approaches to achieve this are used today, legacy PCI bridges lack the required performance and FPGA implementations using on-chip PHYs or external PHY interfaces to PCIe (PIPE) PHYs are often too power hungry, expensive or time consuming to design.
“Like its predecessor, PCIe is moving beyond PCs into embedded and communications systems,” said Jag Bolaria, senior analyst, The Linley Group. “The ability to quickly migrate designs to PCIe will enable manufacturers to take advantage of the market opportunity and leverage FPGAs to provide new functionality in these applications. This is key for applications such as DSP acceleration cards, high definition (HD) video capture and data acquisition cards, which we expect to migrate rapidly to PCIe over the next 18 months.”
GN4124 Exceeds Capability of Legacy PCI Bridge Solutions to Support 1080p60/50 HD Video
The GN4124 typically achieves 3-6x the performance of 64-bit legacy PCI solutions to enable robust multi-channel uncompressed HD video throughput, giving it performance well beyond legacy PCI. With four lanes of PCIe, the GN4124 takes full advantage of the advanced features of PCIe such as virtual channels, full-duplex operation and split transactions. The throughput required to support 1080p60/50 HD video are well beyond what legacy PCI can support today, making the GN4124’s support of these high-performance video rates key for emerging applications. Moreover, the GN4124 is capable of simultaneous HD video capture and playback, which is a capability that PCI solutions cannot match.
Unique GN4124 Reduces Power Consumption by Up to 75 Percent, Features On the-Fly FPGA Firmware Upload over the PCIe Link
The GN4124, with a pin-efficient local bus interface and broad support for industry standard FPGAs, give designers greater freedom to select one to two sizes smaller, lower cost FPGAs to match their application. This can dramatically lower power consumption by up to 75 percent. Additionally, the GN4124 has the unique “on-the-fly” ability to download firmware directly to the FPGA over the PCIe link, which, besides eliminating the need for a separate FPGA configuration memory, enables in-field firmware upgrades and re-configurable computing applications. Most FPGAs available today are SRAM-based and thus require a bitstream download from an external FPGA configuration memory chip or device at every system power-up.
With the ability to upload the FPGA firmware directly over the PCIe interface, the GN4124 gives designers the ability to easily field-upgrade the FPGA code through driver updates or even through on-the-fly reconfiguration, such as changing algorithms. Additionally, the GN4124 enables the designer to eliminate the external memory chip, which results in both cost and board space savings.
The GN4124 can also boot up without the FPGA being programmed, which provides a true live at power-up solution. This eliminates any concerns about a host not being able to recognize an endpoint during the enumeration process because the FPGA bitstream download from external memory is not completed. The GN4124 works with all FPGAs that the support stub series terminated logic (SSTL) I/O standard including:
- Xilinx Virtex and Spartan families
- Altera Stratix, Arria and Cyclone families
- Lattice ECP2/M family
The SSTL local bus interface uses separate 16-bit dual data rate (DDR) transmit/receive busses for full duplex operation. Interface timing closure is simplified by the source synchronous clocking scheme of the DDR interface. This result is the highest possible data transfer rate per FPGA I/O pin with easy timing closure. By minimizing precious I/O resources on the FPGA, smaller, lower cost FPGA package alternatives may be used without sacrificing performance. Advanced features integrated into the GN4124, such as virtual channels, QoS support and multi-threaded buffering provide performance beyond the FPGA cores that are available today.
EN-Genius Says…
Gennum’s GN4124 four-lane Local Bus-to-PCI Express bridge is a great example of how they’ve been applying their mixed-signal expertise to products that make designing with high-speed SerDes technologies easier, faster and less painful. By providing an inexpensive way to add a PCI Express interface to almost any FPGA, Gennum has tapped an important, and under-served market. Now that PCIe is finding increasing acceptance in video and telecom equipment as well as embedded systems and other more specialized applications, designers using FPGAs will appreciate this cost-effective alternative to the premium-priced SerDes-equipped versions of Arria/Stratix- and Virtex-class parts which have dominated the field until now.
As Gennum’s release indicates, the GN4124 connects to its host FPGA via a small local bus IP core. According to Gennum, the logic for the parallel interface requires about 100 k gates to implement. Just for comparison, it would take around 400 k gates to implement the logic for a full PCIe end point. If your application needs to support the full 10 Gbit/s capacity that a quad-lane PCIe connection can deliver, the host FPGA must be able to be clocked at a minimum of 200 MHz. Gennum has also thoughtfully added provisions that allow you to use slower (ie less expensive) parts if your application doesn’t require all that capacity. Designers will also appreciate that the GN4124 has on-chip logic that supports communication with the root complex during enumeration at system boot time. This eliminates any problems that might occur due to the delay in responding to the PCIe enumeration request while an FPGA-based PCIe solution boot-loads its code after power-up. 
Given everything it can do for your design, the $20 that it takes to add the GN4124 PCIe capability to a Cyclone, Spartan, or other value-priced FPGA is a downright bargain compared to the Stratix/Virtex-class parts that offer on-chip SerDes. My back-of-the-napkin estimate is that this combination will give you somewhere around a 4x – 5x savings for many applications that would normally require a PCIE-capable FPGA. And that’s not counting the $3 - $10 you’ll save if you use the host system to initialize the FPGA instead of a boot Flash.
Of course, Gennum’s cost advantage shrinks a bit if you want to use one of Altera’s new value-priced, PCIE-capable Arria devices (reviewed here September 2007). That price differential may evaporate completely, or even go negative, if your application can work with Lattice’s bargain-priced SerDes-equipped ECP2M and SCM PCI Express solutions (reviewed here November 2006). To be fair, the Lattice chips don’t offer anywhere near the signal integrity or full 200 MHz operating speed that the Gennum device does, but if your application can tolerate it they are worth considering. In many applications, however, the GN4124 value-add features and the extra performance margin you get from Gennum well-designed transceivers will still make it the weapon of choice for adding FPGA-based functionality to PCIE-based systems.
Initial pricing for the GN4124 is expected to be $20 per unit based on 10 k quantity volumes and is currently sampling, with full production slated for Q4 2008. A complete reference design is available that includes the GN4124, driver software, and example application code that is well suited to performance benchmarking. Gennum’s royalty-free local bus interface FPGA IP is available to registered GN4124 on their web site. An evaluation platform and reference design specifically oriented towards video applications is expected to be available in early 2009.
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