connectivityZONE Products for the week of September 3, 2007
Altera Corporation Says...
PCI-SIG-Compliant x1 and x4 PCI Express Solution Supporting Arria GX FPGAs
Arria GX FPGA development kit is certified PCI-SI-compliant
Altera Corporation has announced that its low-cost Arria GX FPGA Development Kit has passed PCI-SIG’s compliance tests on its first submission. Altera Arria GX FPGAs, combined with Altera’s PCI Express x4 MegaCore intellectual property (IP) function, are an integral part of the lowest-cost, PCI-SIG-compliant development kit in the industry. The kit provides designers with an ideal platform for developing PCI Express (PCIe), Serial RapidIO (SRIO) and Gigabit Ethernet (GbE) solutions for communications, storage, computing, industrial, medical and consumer applications. Built on a PCIe form-factor card, the low-cost Arria GX FPGA Development Kit delivers a complete environment for developing and testing designs that implement high-speed serial interfaces in Arria GX FPGAs.
"In addition to passing the compliance tests on the first round, our strategy of using our robust and well-proven transceiver technology on low-cost Arria GX FPGAs delivered substantial performance margins," said David Greenfield, senior director of product marketing for high-density FPGAs at Altera. "These performance improvements enabled significant reduction in the kit’s board layer counts to an unprecedented total of six layers, which directly reduces customers’ system costs. Through these achievements, we’ve reinforced our commitment to providing customers with the lowest-risk, lowest-cost, FPGA-based system solutions for PCI Express x1 and x4, Serial RapidIO, and Gigabit Ethernet designs."
Arria GX FPGAs are optimized to support PCIe, GbE and SRIO standards up to 2.5 Gbps. These standards are rapidly emerging as mainstream protocols in a wide variety of markets and applications. Features of the Arria GX family include the proven Stratix II GX transceiver technology, flip-chip packages for superior signal integrity, software tools and verified IP cores.
EN-Genius Says...
Altera PCI Express IP and its brilliant little reference design has given its budget-friendly line of serdes-equipped Arria devices precisely the right weapons it needs to challenge Lattice ambitions to dominate the many high-volume applications where PCIe has become the connectivity technology of choice. Rather than get into a down-and-dirty price war, Arria application engineers have used the extra margin in their robust transceivers to reduce the overall solution cost of PCIe designs by dramatically cutting the number of PCB layers needed to cleanly route the chip signals. If one can believe the crisp eye diagrams being touted by Altera, this could put their somewhat pricier but better-performing chips on an even playing field with Lattice's bargain-priced ECP2M series.
Arria caused quite a bit of a stir back in May 2007) when they hit the market (see my review) to challenge Lattice's ECP2M product line - which was the first reasonably-priced FPGA to offer integrated serdes capable of supporting PCIe, GbE and Serial RapidIO. After sorting through several conflicting stories about Arria’s genetic heritage, it looks like Altera borrowed the robust 6 Gbit/s-capable PMA (physical media attachment) technology transceiver from its Stratix IIGX line while adding a new physical-coding sublayer (PCS) that locked out any possibility of hijacking the sub-$100 chips for use in applications for which the faster, more flexible (and much pricier) premium series was designed.
Instead of the Stratix infinitely-programmable software knobs that allow users to adjust gain levels, Rx EQ slopes, Tx pre-emphasis, and other parameters to their hearts’ delight, Arria has a single pre-set configuration for each application (PCIe, Serial RIO, and GbE) its intended for. But even without the fine-tuning capabilities, hose fire-breathing PHYs plus the low-parasitic flip-chip packaging give Arria lots of headroom at the slower 1 Gbit/s to 2.5 Gbit/s speeds where 80% or more of today’s applications run. My briefers were quick to point out that the flip-chip packaging also a significant contribution to signal integrity by eliminating the Vcc ground sag and simultaneous switching noise that less expensive wire bond packaging can have.
Since Arria high-performance transceivers and packaging added enough to Altera production costs that it would be tough to beat Lattice prices, the apps folks sharpened their pencils and found a way to use some of that performance to shave off some of the PCB layers normally needed to maintain signal integrity in multi-Gbit/s designs. The combination gave them enough link margin to combine signal layers and power routing rail planes to create a six-layer design (four signal layers, one power layer, and one ground) that handles the additional crosstalk and attenuation while still delivering 6 inch to 8 inch of reach (plus one edge connector transition).
By using their extra margin to run comfortably in a sub-optimal channel, Altera has dramatically shaved the number of PCB layers required for a PCIe connection. They claim that the reduced complexity can cut PCB costs by at least 50% and perhaps as much as 75% in higher-volume applications. Since printed circuit manufacturing practices have evolved considerably since I worked with them I am not sure about the precise cost savings that will be realized from shaving off four to eight layers from a mother board, server blade or other PCIe design, but I would not be surprised if it saved as much, or more than what you’d save by buying an equivalent Lattice part.
Of course this assumes you’ll be using an Arria for every serdes connection in your design - something Altera would love you to do but might not be what you had in mind. If the other serdes-equipped components in your design are not capable of supporting the six layer approach that Altera uses, some or all of the cost savings you might realize will be lost, although the extra reach and eye margin that these devices give you will not be.
Altera says that they expect to see most of the early design wins in daughter cards for communications equipment, with a fair amount of activity in industrial, T&M, and medical as well. I’ll speculate that it may also find many early adopters who are involved with µTCA applications as well.
The EP1AGX50CF484C6 device sells for $50 in 25-k piece lots. All Arria GX devices will be in production by September 2007. The Arria GX FPGA Development Kit is also available with a list price of $995.
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