connectivityZONE Products for the week of October 9, 2006
Lattice Semiconductor Says…
90-nm Low-Cost FPGA Family Boasts PCIe-Capable 3 Gbit/s SerDes, Embedded DSP & Encryption Blocks
Lattice Semiconductor Corporation has announced the LatticeECP2M FPGA family, the industry's first low cost FPGAs offering high-speed embedded SerDes I/O plus a pre-engineered Physical Coding Sublayer (PCS) block. Based on the innovative LatticeECP2 low cost architecture, the new LatticeECP2M family also has been developed on advanced 90nm CMOS technology utilizing 300mm wafers. Previously, high-speed embedded SerDes serial I/O with speeds over 3Gbits/s has been available only on relatively expensive high-end FPGAs. Integrating this capability into a low cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video, and industrial equipment. Priced at approximately one-third the cost of competitive SerDes-based FPGAs, the ECP2M FPGA family effectively bridges the price/performance gap between low cost and high-end FPGAs.
The LatticeECP2M devices also have dramatically increased on-chip memory capacity to support higher bandwidth, SerDes-based applications. LatticeECP2M Embedded Block RAM capacity ranges from 1.2 Mbit up to 5.3 Mbits, representing up to a 400% increase over competitive low cost architectures. Both the LatticeECP2 and LatticeECP2M FPGA families offer a comprehensive array of features that includes 375 MHz block level performance, 18x18 multipliers, embedded memory, pre-engineered 400 Mbps DDR2 memory interface support, full-rate (10Gbits/s+) SPI4.2 support, configuration bitstream encryption and dual-boot configuration support. With the addition of 4 to 16 channels of 3.125 Gbits/s SerDes, the LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low cost SerDes capability for PCI Express and Ethernet based chip-to-chip and small form factor backplane applications.
"The LatticeECP2M family charts a new course within the low cost FPGA segment, and sets Lattice apart in terms not only of our product innovation but also our ability to bring heightened value to our customers," said Steve Skaggs, Lattice CEO. "These devices redefine what a low cost FPGA should be, and they will change how customers evaluate FPGAs for their high volume designs."
"Our customers enthusiastically embraced the Economy Plus concept when we introduced it with our first-generation LatticeECP family," said Stan Kopec, Lattice corporate vice president of marketing. "Now, Lattice is breaking with convention by delivering the lowest cost SerDes-based FPGAs in the industry. The LatticeECP2M family and our recently announced Extreme Performance LatticeSC devices now provide the industry's most complete portfolio of high-speed embedded SerDes solutions."
The LatticeECP2M family will include five devices ranging in density from 20K LUTS to 95K LUTS. The number of 18x18 multipliers in the LatticeECP2M family also has been increased and now ranges from 24 to 168. Each device provides two Delay Locked Loops (DLLs) and eight Phase Locked Loops (PLLs) for timing control. The devices will be available in a variety of fine pitch BGA (fpBGA) packages offering 144 to 601 I/O pins and will operate from 1.2volt power supplies.
Cost Optimized SerDes Architecture Provides Rich Feature Set
The LatticeECP2M family maintains all of the compelling features of the LatticeECP2 family, including DSP functionality, that are required for high-volume, cost sensitive applications. The SerDes integrated into the LatticeECP2M has been engineered specifically for implementation in a cost effective, power efficient (power consumption as low as 100mW) quad-based architecture with 1 to 4 quads, depending on the size of the device. Each quad features 4 SerDes channels (4 complete TX and RX channels) and supports data rates from 270 Mbps to 3.125 Gbits/s. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SerDes/PCS combination is designed to support today's most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).
The combination of SerDes, high performance DSP and a low cost FPGA fabric is extremely attractive to Edge and Access system vendors that are integrating these serial protocols into their wireless base stations, radio network controllers, DSLAMs and other last mile aggregation equipment that enable "triple play" technologies. Mass storage, high-speed server, medical imaging and industrial equipment system designers interested in low cost signal processing also will benefit from the LatticeECP2M family's unique combination of features.
Features Common to the LatticeECP2M and LatticeECP2 Devices:
- Optimized Logic and Routing Fabric: The logic block and routing have been optimized for today's high performance FPGA designs and include support for distributed memory (provided on 12.5% of LUTs) and registers (provided on 75% of LUTs).
- Pre-engineered 840Mbps Parallel I/O: Support is provided for DDR memories and other similar standards that require high-performance parallel I/O interfaces within the FPGA. These devices provide DDR mux/de-mux, precision delay and gearbox logic elements that can be combined to implement pre-engineered DDR2 (400Mbps) and other source synchronous interfaces, operating at up to 840Mbps, for applications such as SPI4.2 and ADC/DAC interfaces.
- Full Feature sysDSP Blocks: Embedded sysDSP blocks capable of implementing multiply, accumulate, summation and pipelining functions. The devices can implement DSP functions up to 63,000 Million Multiply Accumulates per second (MMACs).
- Easy Field Logic Update: In order to accommodate bug fixes, respond to changing standards and support the addition of new features and services, an increasing number of FPGA designs require FPGA logic updates in the field. The ECP2M devices provide dual-boot support (the ability to configure the device from two or more configurations in industry standard Serial Peripheral Interface (SPI) PROMs) and Transparent Field Reconfiguration (TransFR) I/O to simplify field updates. TransFR I/O capability allows designers to precisely control I/O states while a new configuration is loaded into the FPGA, a significant improvement over the more conventional practice of tri-stating I/Os during reconfiguration.
- Bitstream Encryption for Enhanced Design Security: To address increasing design piracy concerns, the devices have on chip non-volatile key storage and decryption circuitry to allow the decryption of 128-bit AES encrypted bitstreams based on a unique user key.
Design Tools and Intellectual Property Support:
- Design support for the LatticeECP2M devices is provided by the latest version of Lattice's ispLEVER design tool suite, Version 6.0 SP1. The ispLEVER design tools provide access, in one software package, to all Lattice digital devices and include synthesis support from Mentor Graphics and Synplicity. As with the LatticeSC devices, a convenient module-based GUI (graphical user interface) greatly simplifies configuring the SerDes.
- Customers also will have easy access to key ispLeverCORE Intellectual Property modules through the IPexpress design flow. IPexpress-supported functions will include PCI Express, SGMII, DDR1 and DDR2 memory controllers and SPI4.2.
EN-Genius Says . . .
Lattice's new low-cost product line with integral SerDes puts them on a collision course with the two big dogs in the FPGA arena, most notably Brand A who has done very well with its high-end StratixII GX SerDes-enabled devices. The last few years since has seen the emergence of FPGAs that are now inexpensive enough to use in high-volume cost-sensitive applications but, until now, there has always been a big price/performance/feature gap between these ultra-low-cost (ECP/Spartan/Cyclone-class) products and the SC/Stratix/Virtex-class high-end devices. This has changed with Lattice's new product family. While they can't touch the upper speed limits and jitter performance Altera offers (more on this later), they pose a big threat by being good enough to support the PCI express and Gigabit Ethernet interfaces that are used in many high-volume applications at a cost ($0.65 - $1/LUT) that its competitors cant match.
 The new FPGA family also includes larger embedded block RAM (up to 5.3 M), encryption acceleration logic and hardware multiplier elements (nicely described in the release above), but the big news here are the 3.125 Gbit/s Ser Des cores. They support up to 16 channels of most the popular serial I/O technologies including PCIe, GbE, SGMII, and two slower forms of SRIO without any external PHY-layer or CDR devices (see Fig. 1). The cores include dedicated physical layer encoding/decoding sublayer (PCS) logic to conserve precious LUTs. Lattice was quite clear that the current devices did not support XAUI interfaces due the to relaxed jitter performance of the simpler, lower-power CDR cores they used to meet their aggressive price/power targets. The designers managed to keep the transceiver's power down to 100 mW/channel by using an all digital CDR, and a relatively simple 12 dB linear receive EQ.
Lattice has made a smart, if painful, strategic set of trade-offs here. While the fully-digital CDR can maintain its clock within specification for far longer than the worst-case 10-bit non-transition period (ie 10 consecutive zeroes) required to support 8B/10B coding, eliminating the power-hungry analog PLLs in the CDR shortens the circuit's attention span to far less than the 72 consecutive zeroes required for SONET/SDH. Since doing this slashes the CDR core to about one-third the size of the robust block used in Altera's rock-solid Stratix II GX SerDes (reviewed here November 2005), the lower performance is understandable and appropriate for the intended applications.
The result is an FPGA series that's well-suited for high-volume applications which employ 8B/10B-coded SerDes interfaces such as cellular base stations, broadband access infrastructure (DSLAMs, PON boxes, WiMAX, etc), and server-based products using PCIe. With the proliferation of PCI express in ATCA/uATCA products, I expect Lattice's LatticeECP2M to end up supplying custom functionality and bridging functions on lots of blades and mezzanine cards.
All this sounds very promising, and from what I know about 90-nm CMOS processes, Lattice's claims seem quite believable. But, given the fact that this is Lattice's first venture into multi-Gigabit SerDes and more than one company has stubbed its toe on the technology (both performance and yield), I'd caution you to get some samples and make sure they meet your requirements before designing them in. Between these considerations and the fact that I am less familiar with the company than I'd like to be and have not had a chance to see running silicon myself, I'll add a half-saltshaker to my Vapor Index Rating. But even the 2 saltshakers they earned should tell you that it's a good bet that Lattice can deliver on most, or all of its promises.
And if you are using Latttice's FPGAs the new 32-bit processor core IP that was released at the same time as the ECP2M is also worth taking a look at. It expands the previous MICO embedded 8-bit architecture to 32 bit while maintaining the same open-source approach to the code, which allows developers to take advantage of a large existing user base and huge code base. The basic processor takes 2 k LUTS to implement -- about $1 - $2 worth of silicon, with another 500 LUTs each or less to for any fancy peripherals (timers, UARTs GPIO and memory controllers) you care to add. If this intrigues you, you can find out more from the press release posted on Lattice's web site.
The first member of the LatticeECP2M family, the LatticeECP2M-35, in both BGA-484 and BGA-672 will sample in October 2006 with production in the first half of 2007 and pricing as low as $22.95 in 100-k piece lots.
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