connectivityZONE Products for the week of October 16, 2006
Xilinx Says…
Xilinx Delivers Virtex-5 LXT FPGAs With Industry's First Built-In PCI Express Block And Low-Power Serial I/Os
World's first 65-nm FPGAs with hardened protocol blocks and easy-to-use solutions take serial connectivity mainstream
Xilinx, Inc. has announced initial shipments of its Virtex-5 LXT FPGAs. The second of four domain-optimized platforms in the new Virtex-5 family, the LXT platform series is the first FPGA to deliver a hard-coded PCI Express Endpoint and Tri-mode Ethernet Media Access Controller (MAC) blocks. The Virtex-5 LXT platform also features the industry's lowest power 65-nanometer (nm) transceiver, typically consuming less than 100mW per channel at 3.2 Gbits/s.
Xilinx has engaged with several customers in its early access program since June of this year. "Agilent's high-end instruments are built for emerging markets and require a SoC platform with high-bandwidth connectivity and the time-to-market advantages of FPGAs," said Mr. M. Heinen, R&D section manager at Agilent, one of a select number of early access customers. "TheXilinx Virtex-5 LXT platform provides us with the system performance we need, along with low-power and high-speed interfacing enabled by the 3.2 Gbit/s transceivers. Pin compatibility across multiple platforms allows us to scale up our design for future needs."
Triple Play Drives Mainstream Adoption
The Virtex-5 LXT platform addresses the challenging bandwidth, power and cost targets facing equipment vendors working to enable the emerging 'triple play' services market (voice, video and data over single broadband Internet Protocol connection). The new platform is optimized to enable FPGA designers across a wide range of applications to benefit from serial connectivity by delivering a comprehensive, fully compliant protocol solution with the greatest ease of use.
"What started in the communication segment to improve bandwidth, cost and scalability is now becoming an industry-wide migration from parallel to serial interfaces across many applications within wired/wireless, video, storage, servers and consumer. A one-size-fits-all FPGA approach is no longer sufficient," said Steve Douglass, vice president of Product Development at Xilinx. "The Virtex-5 LXT platform is the first of several high-speed serial platforms to be offered in the Virtex-5 family. The LXT platform is aimed at the large number of serial connectivity applications ranging from 100 Mbits/s to 3.2 Gbits/s."
Industry Analysts Agree
In the multi-standard serial interface market, PCI Express and Gigabit Ethernet have emerged as the leading interface standards in markets served by FPGAs and are expected to account for over 80 percent of all port shipments in 2009.
"The industry is clearly adopting high-speed serial technology as the preferred connectivity solution. Serial provides better bandwidth, cost, power and scalability than alternative parallel interfaces," said Steve Berry, principal analyst at Electronic Trend Publications. "Xilinx has established itself as the industry's premier supplier of high-speed connectivity solutions through several generations of products, and their Virtex-5 LXT platform raises the bar even higher by providing solutions in the sweet spot of the market to a much broader community of designers."
Virtex-5 LXT Platform
The Virtex-5 LXT platform delivers the industry's first FPGA to offer a built-in PCI Express Endpoint block and tri-mode Ethernet MAC, which gives designers an off-the-shelf solution that saves time, reduces power consumption and frees up valuable FPGA fabric resources. Built on the 65-nm Virtex-5 platform with new ultra-fast ExpressFabric technology, proven ASMBL architecture and low-power triple-oxide technology, the Virtex-5 LXT platform delivers an average of 30 percent higher performance, 65 percent increased capacity and up to 35 percent reduction in dynamic power consumption over previous generation 90-nm FPGAs. The hardened PCI Express core saves users up to 10,000 LUTs and two watts of power as compared to soft intellectual property (IP) core implementations.
Key features and innovations of the Virtex-5 LXT family include:
- Industry's lowest power transceivers: up to 24 RocketIO transceivers operating from 100 Mbits/s to 3.2 Gbits/s typically consuming less than 100mW per transceiver/receiver pair.
- Built-in PCI Express block: fully compliant endpoint block that works with the RocketIO GTP transceivers to provide x1, x2, x4 and x8 PCI Express interfaces.
- Built-in tri-mode Ethernet MAC blocks: four independent 10/100/1000 Mbit/s blocks that work seamlessly with RocketIO transceivers.
- Industry's best signal integrity: eight programmable levels of Transmit Pre-emphasis and four programmable levels of Receive Equalization address even the most stringent channels.
- Advanced diagnostic capability with the Chipscope Pro software toolset gives engineers the best signal integrity solution available.
- Widest protocol support: the Virtex-5 RocketIO transceivers support a myriad of industry standards including PCI Express, Gigabit Ethernet, XAUI, SONET/SDH, CPRI and OBSAI, Serial RapidIO, HD-SDI and Fibre Channel.
- Off-the-shelf design solution: complete protocol-based solution consisting of software, IP cores, reference designs, development kits, characterization reports, protocol compliance certification, collateral and design support.
EN-Genius Network Says . . .
Xilinx was smart to include a series of devices with native PCI Express (PCIe) capability in their new 65-nm Virtex 5 FPGA family with the LXT series of devices because it addresses so many markets that are adopting it as their interface of choice. While their earlier V4 series could support PCIe using a soft MAC, the V5 LXT family's hard MAC IP (for both PCIe and tri-mode GbE) embedded in the chips saves both power and programmable gate count -- commodities that are usually in short supply in any design. And if you have need of some other SerDes-based interface, you can bypass the hard cores and implement a MAC for CPRI/OBSI, OC-4, SRIO or nearly any other 2/5 - 3.125 Gbit/s standard that does not have a SONET/SDH spec attached to it.
Xilinx claims that power consumption for one of their new 3.2 Gbit/s PCIe SerDes transceivers is under 100 mW. Even adding in a possible 20% fudge factor (to compensate for their occasionally overly-optimistic claims), it's still a huge improvement over their earlier V4 chips whose 6-Gbit/s SerDes transceivers chewed up around 350 mW -- even running at 3.125 Gbit/s. These next-gen V5 devices have been put on a lean-and-mean power diet, beginning with a simpler transceiver architecture which uses a straightforward linear receive EQ with 4 programmable levels. The transmitter section has a simple 8-level pre/de-emphasis circuit which is also quite power-frugal -- and very appropriate for the sub-5 Gbit/s applications that these devices address.
The transceiver's lower operating speed also enabled significant power savings by narrowing the CDR VCO's operating range and using the faster transistors available in the 65-nm digital process to replace some analog elements of the CDR with digital equivalents. Xilinx's final power-saving trick was to share a single PLL between each Tx and Rx pair -- a choice which limits some design options for exotic applications, but should not cause a problem with the vast majority of designs these parts are intended for.
The fact that Xilinx delayed the official roll-out of this first V5 family of FPGAs until they'd been in customers' hands for a couple of months indicates that they've learned some hard lessons from the yield disasters they had on their early SerDes-equipped V4 products and are making sure that doesn't happen again. They've also gone through the trouble to provide full characterization of the devices' critical parameters for both overall performance and for specific applications like PCIe, XAUI and SRIO. Having this data should give you the ability to perform up-front analysis of link margins, jitter budget and obtain other important clues to how your design will actually work. This characterization data is included with a series of solution-kits that give you a full reference design for a particular application. The kits also include compliance-certified reference designs and evaluation boards, pre-verified IP cores and application-specific design software to configure the SerDes transceivers.
If the SerDes elements in Xilinx's V5 series can actually deliver the performance and power savings they claim, it could help them compete with the robust Stratix IIGX SerDes-equipped FPGA series (reviewed here November 2005) produced by their arch-rival, Altera. From the specifications I was given, Xilinx seems to enjoy an advantage over Altera's general-purpose SerDes which consume 125 mW running at 3.125 Gbit/s, and require somewhere around 7 - 10 k LUTs worth of logic to build a soft PCIe MAC.
Unfortunately, since Xilinx was reluctant to share enough details of their transceiver architecture, it's still not clear to me whether they actually have the reach, signal integrity, and jitter performance of the Altera parts. I say this because besides providing me with the architectural details of their IIGX transceivers, I've also been able to spend some hands-on time in the Altera labs. The demonstrations I witnessed (and a few of my own measurements) of their devices running at up to 6 Gbit/s under all sorts of ugly, close-to-real-world conditions confirmed Altera's claims for performance, margin, and power consumption. Despite any misgivings I noted above, I'd expect that the V5 LTX series will be great for many applications, but it will be the engineer's judgment call if Xilinx's power and gate savings will be worth trading off the extra margin that I believe Altera's transceivers offer.
Of course, Altera is not the only company that should be keeping Xilinx up at night.
Lattice Semi has recently introduced additions to their lower-cost ECP series which have integrated PCIe-capable transceivers (reviewed here October 2006). To be honest, the eye diagrams I saw indicate that Lattice's transceivers don't have the performance found in either the Xilinx or Altera devices and begin to show sharp roll-off as they approach 3 Gbits/s. And, as with the Altera parts, you'll have to sacrifice some of your logic elements to implement the MAC of your choice. But when you consider that Lattice's smallest (20 k LUT) ECP part is priced at about 25% of what an entry-level V5 LTX device costs, this good-enough design philosophy may indeed be good enough for many less-demanding, high-volume applications.
I didn't bring up Lattice's products to run down the Xilinx products I'm reviewing here, but felt they were important to mention because the rapid acceptance of PCIe is creating huge market opportunities in high-volume products whose total BOMs may just barely equal the $100+ prices of either Xilinx's or Altera's current SerDes-capable product lines. While there will always be a steady demand in higher-ticket applications such as audio/video encoding and processing, smart bridging, and DSP acceleration, Xilinx will be leaving money on the table if it does not find a way to offer similar capabilities on its lower-cost Spartan product series. When I inquired about this with Xilinx, the representative offered a simple "no comment."
Software support for the Virtex-5 LXT platform is available now. Virtex-5 LXT engineering samples are shipping now. Production will start in 2007 and for deliveries in 2008, the LX30T will list for $109, the LX50T for $189 and the LX110T for $529 in 1000-piece lots.
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