 connectivityZONE Products for the week of November 7, 2005
Altera Corporation Says…
Altera's Latest FPGA Family Boasts Embedded Transceivers That Deliver Lower Power, Superior Signal Integrity
Altera Corporation has launched the Stratix II GX family, its third generation of FPGAs with embedded serial transceivers. Designed to deliver superior signal integrity, Stratix II GX FPGAs offer a complete programmable solution for the growing number of applications and protocols requiring high-speed serial transceivers. Stratix II GX FPGAs combine the industry's fastest and highest-density FPGA fabric with up to 20 low-power transceivers that operate between 622 Mbits/s to 6.375 Gbits/s to meet the requirements of high-speed designs of today and tomorrow.
Altera carefully selected the data range of the Stratix II GX transceivers based on customer requirements and future protocol roadmaps. The transceiver blocks provide complete support for a number of widely used protocols, including PCI Express, serial digital interface (SDI), XAUI, SONET, Gigabit Ethernet, SerialLite II, Serial RapidIO, and Common Electrical Interface 6 Gbits/s Long Reach and Short Reach (CEI-6G-LR/SR), saving valuable logic resources and simplifying protocol support. Additionally, designers can complete their designs quickly and efficiently by utilizing Altera's comprehensive system solutions that include intellectual property (IP), system models, reference designs, signal integrity tools, and supporting collateral.
Stratix II GX Features
Stratix II GX FPGA features help designers simplify the complex task of designing systems that use high-speed protocols. These features include:
- Multi-Gigabit Transceiver Blocks: Stratix II GX FPGAs provide up to 20 full-duplex channels operating between 622 Mbits/s and 6.375 Gbits/s natively and down to 270 Mbits/s using over-sampling techniques.
- Signal Integrity: Stratix II GX transceivers optimize the data eye opening using on-chip, dynamically programmable transmit pre-emphasis, receive equalization and output voltage control. In addition, through enhanced packaging and chip-design optimization techniques, standard I/Os are designed to provide best-in-class signal integrity.
- Low-Power Transceivers: Stratix II GX FPGA transceivers consume only 225 mW per channel at 6.375 Gbits/s, less than half that of the nearest competing FPGA solution.
- Flexible Transceiver PLL & Clocking Modes: Stratix II GX FPGAs arrange transceivers in a quad implementation. Each quad can be driven by two different clock sources each with access to a high-speed and a low-speed phase-locked loop (PLL). This combination of clocks and PLLs supports four different data rates and dramatically reduces power dissipation compared to the single PLL implementation found in competing devices.
- Up to 132,540 Equivalent Logic Elements (LEs) and up to 6.7 Mbits of Embedded Memory: The Stratix II GX devices' high-density and embedded memory complement the bandwidth and performance of the device transceivers.
- Industry-Leading FPGA Architecture: Built on TSMC's industry-leading, production-qualified, 90-nm process technology, the Stratix II GX family is based on the same FPGA fabric as the Stratix II FPGA family that offers unparalleled, and proven, density, performance, logic efficiency and design security.
"Customers are already leveraging the best-in-class signal integrity of the previous Stratix GX family and the performance and density advantages of the Stratix II family. In Stratix II GX FPGAs, we've extended the best features from these device families to meet the needs of the marketplace over the next several years," said Danny Biran, vice president of product and corporate marketing at Altera. "System engineers using Stratix II GX FPGAs, along with the complete solutions that we've built around them, have a highly-efficient, low-risk development path for their high-speed designs."
"Our goal is to deliver complete interconnect solutions that are robust and exceed demanding requirements for performance, reliability and value," said Tom Pitten, vice president of engineering and marketing at Teradyne Connection Systems. "The work we have done with Altera in validating the entire interconnect continues to support this goal and provide system designers with solutions of exceptional signal integrity at leading-edge data rates."
"Our collaboration with Altera in developing and correlating tools that enable modeling, design and manufacturing of robust serial interconnects has yielded excellent results," said John D'Ambrosia, manager, semiconductor relations, Tyco Electronics. "Customers adhering to design methodology recommendations for Stratix II GX FPGAs and Tyco interconnect solutions can expect excellent signal integrity results."
EN-Genius Network Says . . .
There are several key features in Altera's new StratixII GX FPGA family which indicate that, much like their arch-nemesis, Xilinx, they've determined to move aggressively into selling system-level solutions rather than just being the "glue" that designers traditionally add at the end of a design effort. While the entire Stratix II family boasts much larger available MRAM blocks and a large library of licensable IP, including a very fast-efficient RISC core, their recent introduction of new high-performance SerDes cores and signal integrity features for their "GX" series are the things that really jump out at me as significant potential differentiators.
In addition to the high-speed parallel IO (up to 1.25 Gbit/s LVDS/SSTL/HSTL) and configurable interfaces found throughout the Stratix II product line, the GX series substitutes one of the banks of parallel interfaces for up to five banks of four configurable SerDes transceivers capable of running at up to 6.375 Gbit/s. Each block contains its own transmit/receive, clocking and coding circuits, plus programmable equalizer and pre-emphasis blocks. As we'll shortly see in a bit more detail, the SerDes block's timing section includes pair of central PLLs that can be divided at will to derive different clock rates.
The hardware SerDes elements are wrapped together with what Altera calls "targeted protocol solutions", which are collections of IP that can be blown into the FPGA's logic to support almost any standard or proprietary serial interconnect with rates up to 6.5 Gbit/s. The current library includes "recipes" of protocol-specific MAC logic as well as a collection of hardware state machines that support speed/timing critical functions such as PCIe PIPE, low-level XAUI functions, and SONET scrambling. The result is a do-it-yourself kit that lets you create transceivers for PCIe, CEI 6G (OIF), GbE, Serial RIO, XAUI, SDI-HD/SD, and SONET/SDH at both OC-12 and OC-48 rates. There is even a set of IP for implementing what Altera calls 3- and 6-Gbit/s "basic mode" devices that allow customers to quickly add their own specialty protocols on top of the PHY layer.
Of course, "Brand X" also has high-speed SerDes cores on many of its Vertex IV series (reviewed here and here) which can be used for similar purposes. And while I have lots of respect for the excellent work Xilinx has put into their interfaces, it appears that Altera (at least for the moment) delivers better specs in terms of power consumption and overall performance. The two biggest areas that differentiate their Stratix SerDes elements are in their PLL/CDR design and the transceiver equalization technology they use to achieve better signal integrity, reach, and overall performance under realworld conditions.
Altera's transceivers feature an equalization scheme with transmit pre-emphasis and receive equalization elements that are sophisticated enough that they'd likely enjoy good commercial success as standalone parts. The receive EQ is a programmable multi-stage linear analog system, with each stage enjoying independently programmable gain (up to 80 dB total), slope and corner frequencies. The programmable transmit pre-emphasis system is also rather novel, with provisions for separate adjustments of a symbol's leading and trailing edges. In addition to one-tap worth of precursor control, it has a two-tap trailing edge active filter that that avoids post-cursor-induced smearing (ie ISI) of the subsequent bit. Together, they provide both de-emphasis of low frequencies and pre-emphasis of high frequencies that, at least theoretically, achieves 800 mV worth of eye opening on a 40 inch FR-4 backplane.
Of course all that programmability can be a potential drawback. Running through all 5 k+ possible PE/EQ settings to find the best combination for your particular application could take days, or even weeks. To spare you this pain, Altera has thoughtfully provided a Matlab tool that allow users to supply the S-parameters for a particular channel and get the perfect settings within 45 minutes.
The second element of Altera's strategy is a PLL architecture that delivers impressively low power and jitter specs. Part of the success lies in the fact that they use two separate PLLs in each Quad SerDes block to split frequency management duties between the 600 MHz-to-3.2 Gbit/s and 2.5-to-6.375 ranges. This keeps their control loops narrower with, as you'd expect, lower jitter. Altera also introduced on-chip voltage regulation which eliminates packaging inductance and susceptibility to supply noise caused by current draw from other elements of the device. Besides lowering overall BOM costs, it also reduces supply-induced glitches in the clocking circuit.
When combined you get an array of SerDes elements that can pass stringent SONET jitter generation and jitter requirements quite nicely. They even meet the basic jitter transfer specifications as standalone transceivers although adding a few of the chip's PLD elements to the signal chain takes it over the limit for a single regenerator node. Fortunately, jitter transfer is not a critical spec in simple backplane and other "non-line" applications.
The PLLs have also been aggressively engineered to reduce overall power consumption. While I'm not at liberty to discuss all the design tweaks that Altera applied to them, I can tell you that their VCOs and other critical analog functions were built from a custom library of high-speed cells with a highly granular palate of drive currents. This allowed Altera's silicon cowboys to use just enough power to do the job at every stage in the signal chain. Altera also saved a lot of power through careful attention to clock distribution. Centrally locating the high and low speed clock elements in each quad SerDes block and balancing the signal paths helped to minimize path loss, loading and skew as well as reduce drive current requirements.
The combined effect of all these details is pretty significant, producing transceivers that draw a mere 125 mW running at 3.125 Gbit/s and 250 mW running flat-out at 6.375 Gbit/s. This compares very favorably with Xilinx's published spec of 425 mW and 550 mW respectively. And if you don't think these savings are significant, consider you're your equipment will run 6 W cooler for every 20 channels worth of SerDes you have.
Their lower power, excellent reach, and an extremely wide speed range should enable the Stratix II GX FPGA family to find a "sweet spot" in many current popular applications requiring SerDes, as well as many of the faster technologies which are anticipated to be commercially significant for at least the next two years. And with all the design tools available and pricing as low as $49, we can expect these little critters will pop up in lots of unexpected places including networking gear and perhaps even high end consumer electronics.
The first member of the Stratix II GX family sample in Q1 2006. Volume pricing will start at $49. HSPICE models and Altera's Quartus II design software version 5.1 are available.
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