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connectivityZONE Products for the week of November 24, 2008
Lattice Semiconductor Says…
Industry’s Leading Hardened SPI4.2 Solution Portfolio
Low Cost, Low Power SPI4.2 Cores Bolstered With Enhanced Buffer Management Features
Lattice Semiconductor Corporation has announced that its industry-leading LatticeSCM FPGA family-based SPI4.2 MACO (“Masked Array for Cost Optimization”) cores have been enhanced by adding sophisticated link layer buffer management options. Compared to competitive FPGAs, the LatticeSCM FPGA family has offered the industry’s most feature-rich SPI4.2-based cores and bridge reference designs at the lowest cost, power and printed circuit board footprint. These new features enhance this solution portfolio by allowing designers the option to use a parameterizable buffer manager for applications needing per-channel bandwidth management.
“We continue to enhance our SPI4.2 solution portfolio by integrating sophisticated system-level features, while maintaining the low cost and power targets that have made Lattice a leading SPI4.2 programmable gasket solution provider,” said Shakeel Peera, Director of Strategic Marketing for SRAM FPGAs. “Designers working on 10G Carrier Ethernet and Packet over SONET platforms will find these features useful as they architect systems designed around determinism and Service Level Agreement (SLA) guarantees.”
The LatticeSCM FPGA platform provides designers with multiple hardened SPI4.2 cores using Lattice’s exclusive MACO structured ASIC technology. MACO technology delivers pre-engineered, standard-compliant IP functions, developed by Lattice, that shorten end-system time to market and dramatically lower device cost, power and PCB footprint targets. These new features provide designers with a programmable buffer manager capable of:
- Up to 16 separate physical FIFOs per TX/RX direction
- Packet over-flow and error drop
- Both store & forward as well as cut-through operation
- Parameterizable buffer depth and thresholds
- Dynamic channel provisioning
- Programmable sequencer-based scheduler
EN-Genius Says…
Although it’s slowly being eclipsed by more sophisticated interconnect standards like SPAUI and Interlaken, the SPI4.2 interface is still probably the most commonly-available connection on network processors, traffic managers and other applications requiring a between PHY and Link Layer devices. It’s no wonder then that Lattice has invested considerable resources to update the existing SPI4.2 capabilities lurking in its LatticeSCM family of SerDes-equipped hybrid FPGAs. By giving the LatticeSCM family enhanced traffic buffering and management capabilities they’ve moved the device beyond a simple gasket/glue function to a system element that can help support advanced QoS/SLA schemes. And since most of these features are implemented in the metal-programmable portion to the ‘SCM’s hybrid FPGA structure, you get them at virtually zero cost.
 In case you’re not familiar with the LatticeSCM hybrid architecture, it’s a unique blend of Lattice’s traditional Programmable Function Unit FPGA blocks, assorted RAM and I/O elements, and blocks of metal-programmable logic. With up to 50 k gates worth of hard logic (the equivalent of around 10 k LUTs ) available in each structured ASIC block, Lattice is able to produce application-specific versions of its SCM devices that contain high-value fixed functions without wasting precious programmable gates. Lattice also offers other versions of the SCM family which use the hard cores and the device on-chip SerDes transceivers to implement PCI Express or Ethernet interfaces. Another version sports the structured ASIC cores to implement flexible memory controllers that can talk to SRAM, DRAM, or RLDRAM chips.
Lattice has implemented 90% of the SPI 4.2 function in hard metal-programmed logic, leaving the buffer manager functions programmable in FPGA gates so that designers can easily adapt the interface to their application’s particular requirements. The result is a SPI4.2 connection that uses 25% to 12.5% of the power and 10% the silicon area of competing solutions using programmable gates.
With all those programmable gates available, it’s easy to build a shim/gasket adapter device such as the SPI4-toXAUI/HiGig bridge, a XAUI to SPI4.2 bridge, or something more ambitious that also does some processing and traffic management. The enhanced queuing and scheduling capabilities offered by the new SPI 4.2 logic could go a long way to offloading a network processor from some lower-level traffic management tasks or providing some very intelligent buffering between system elements. I suspect that, in some cases, the SCM programmable logic could be used to build whatever traffic management or processing function you need, eliminating the need for a separate device.
In moderate production quantities (25 k units), pricing for the LatticeSCM family begins at $17 each for the SC15, their smallest device. Housed in an FPBGA-256, the SC15 has 139 IO lines, 4 SerDes channels and 4 MACO blocks. The SC40, a midrange device, is available in an FCBGA-1020-ball has 562 IO lines, 16 SerDes channels and 10 MACO blocks and is priced at $71 (also 25-k piece lots).
Product Page MACO Core
Product Page LatticeSCM
Product Page SPAUI Solutions
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