connectivityZONE Products for the week of December 13, 2004
Agere Systems Says…
Agere Systems' 90 & 130-nm SerDes Cores Run At 6.25 Gbit/s, Save Power And Silicon Real Estate In Backplane, Storage, And Networking ASICs
Agere has announced a new technology platform for high-speed serial interfaces in storage and enterprise network products. This semiconductor technology enables disk drive and system manufacturers to design interface solutions across any serial standard for increasing the data throughput up to 6.25 gigabits-per-second (Gbits/sec) between devices in computing, mobile, Ethernet networking and network- and server-attached storage applications.
Agere's new serializer-deserializer (SerDes) platform addresses the proliferation of serial interface technology across multiple applications, from emerging Serial ATA (SATA) and PCI Express standards used in PCs to Serial-Attached SCSI (SAS), Fibre Channel and Gigabit Ethernet solutions in enterprise backplane and storage area networks. All of these market segments require the use of SerDes technology to drive serial connectivity.
With power consumption and core size half that of previous Agere serial interface offerings, this SerDes solution delivers a tested and validated platform for single-chip serial integration. Along with exceptional performance, Agere's SerDes architecture offers unprecedented design flexibility. Agere's solution supports both ends of the interconnect for drive-side and host-side serial chips. Serial interface silicon can be developed using both 130-nanometer (nm) and industry-leading 90-nm CMOS process technologies, covering all possible oxide, dielectric and voltage combinations. Agere's solution also offers unique test features that can be used for efficient and comprehensive production testing as well as for system-level testing and optimization, resulting in robust system designs and more reliable data transfers.
"Agere's SerDes solutions will target high-end networking and datacom switch fabrics along with enterprise storage markets where OEMs look to upgrade the bandwidth of existing backplanes and interfaces," said Sean Lavey, program manager at industry analyst firm IDC. "We believe chip suppliers with cost-optimized and low-power serial technology capable of scaling from today's 2.5 and 3.125 Gbit/sec speeds to faster 6.25 Gbit/s speeds will be positioned well for this upcoming transition."
IDC expects that nearly 50 percent of all enterprise disk drives shipped in 2005 will incorporate serial interfaces, with that number growing to more than 90 percent by 2008. In addition, IDC projects the enterprise storage semiconductor market to grow from $857 million in 2004 to $1.2 billion in 2008, while the Gigabit Ethernet (GbE)/10 GbE chip market to grow from $970 million this year to $2.5 billion in 2008 where this class of serial link technology will be used.
SerDes technology takes parallel lanes of data bit streams and converts them to a single stream of high-speed data running serially -- one bit after another -- for more efficient transmissions. SerDes also simplifies system design by eliminating routing congestion and lane-to-lane skew problems that exist in parallel bus implementations. Agere's configurable physical-layer SerDes can be used in application-specific integrated circuits (ASICs) for host bus adapters, enterprise routers and switches, and combined with Agere's TrueStore read-channels and other electronics, to develop storage SoCs and controllers for disk drives.
Industry-leading performance, power, size and production testing
With data rate support of up to 6.25 Gbit/sec, Agere's SerDes solution meets current and next generation requirements of a wide variety of serial interface standards, including SATA, SAS, Fibre Channel, PCI Express, XAUI, SONET backplane, Serial RapidIO and others. A higher level of digital functionality in this new SerDes architecture contributes to a 50 percent reduction in core size and power consumption, and provides for future implementations that support data rates exceeding 10 Gbit/sec.
"With this platform, Agere is offering serial technology that rivals the industry in power savings, small size and data throughput speeds," said Necip Sayiner, vice president of Agere's Enterprise and Networking division. "Agere's flexible platform and production test capabilities provide developers of serial interface products with substantial time-to-market savings, design portability and improved reliability for whatever serial interface standard they choose."
The serial interface platform offers advanced production test features to ensure data throughput reliability and robust silicon designs. Agere has enhanced its leadership in "at-speed" production testing with the addition of asynchronous jitter tolerance test capabilities in this new SerDes platform, allowing for cost-effective core logic and clock data recovery loop testing without the need for additional equipment. Agere's SerDes solutions can perform adaptive equalization, enabling systems to continually monitor and adjust signal quality while running live data. This solution is also unique in offering a 90-nm SerDes architecture capable of both non-return to zero (NRZ) and pulse amplitude modulation schemes.
The SerDes architecture is equally optimized for small or large port count ASICs, and supports a wide range of I/O supply voltages, from 1.8 to 3.3 volts. Agere's solution also enables cost-effective wire-bonding up to 6.25 Gbit/s, and supports flip-chip and lead frame package designs.
Agere leadership in serial development
This new platform expands Agere's expertise in high-speed serial interface technology. Agere has numerous storage-based designs with customers for SATA and SAS hard drive and host controller chips. Agere is also using this serial platform to design 90nm and 130 nm-based Ethernet router and switch ASICs with SerDes capable of running up to 6.25 Gbit/sec.
EN-Genius Says . . .
This new line of SerDes cores complements Agere's extensive line of networking and storage-related IP, something which should go a long way towards keeping both their ASIC and merchant silicon designs competitive. Besides having significantly lower power consumption and a smaller footprint than their previous core, they claim it produces a cleaner transmit eye. This is achieved using a combination of a more stable transmit PLL and giving the analog section of the transmit section better frequency response.
While Agere would not confirm it, I'm guessing the transmit section and receive functions use sophisticated equalization technologies that are at least partly derived from their association with Accelerant -- the SerDes chip manufacturer that was recently acquired by Synopsis. I say this because the DFE-based adaptive equalization used in the core's receiver was a signature element of the Accelerant chips. Another feature reminiscent of Accelerant designs is the three-tap programmable FIR on the transmit side to provide programmable pre-emphasis. Of course, Agere has added its own touches like programmable poles and zeroes in the receive-side preamplifier to provide active filtering ahead of the equalizer.
The folks at Agere I talked to about the core would not give me all of the details on how they did it, but explained that they achieved much of the power savings in their new SerDes blocks by moving from their earlier analog-centric architecture to a more digitally-oriented one. They also explained that their earlier generation design was 90% analog, compared to the 20% analog content of the new cores. Much of the savings is reported to come from the CDR section of the design which eliminated several power-hungry PLL circuits.
The savvy siliconistas of Allentown wisely used the SerDes re-design exercise as an opportunity to make several important strategic moves which will give the chip maker much more agility to respond to future market requirements. For one thing the shift to a mostly-digital design allowed them to cordon off the chip's analog sections. This allows the bulk of the chip to be synthesized for easy migration between 130 nm and 90 nm fab processes today, and paves a path for re-use at 65 nm. The core's flexibility allowed hooks to be left in the basic design (not currently enabled) to support faster transmit speeds. The current analog section is fast enough to support 8.5 Gbit/s FibreChannel, or even 10-Gbit/s Ethernet, and the digital section will only need minor tweaks to match that speed -- something that's most likely occur in very complex products that require a 90-nm process.
Agere's designers also recognized that SerDes is becoming the interface of choice in so many applications and that they had to apply some system-level thinking to optimize their core to work well in highly-integrated merchant and ASIC chips. This included keeping the core size down while making sure that the PLLs were sufficiently shielded to keep them from inadvertently locking on each other when packed together in multi-lane environments. They also thought "outside the chip" and co-designed the driver circuits with their next-gen packaging systems. The result is a layout that has provisions to enable efficient pin-outs for easy implementation of multiple lanes of balanced pairs, that make the transition between the chip and the PCB trace in such a way as to minimize difficult crosstalk, layout, and via issues.
The Agere/Accelerant collaboration I mentioned earlier is also evident in the extensive on-chip signal analysis capabilities that can accurately measure eye margin. The ability to measure both horizontal and vertical eye closure allows you to analyze phase and voltage margins for incoming signals and is handy for measuring overall system performance. The SerDes core also features an analog test bus which provides buffered versions of several important internal signals for use with production ATE or field diagnostic work. I suspect that a clever designer could make use of these smart features in their product to allow equipment to monitor and compensate for critical signal parameters, and or alarm on them if they went too far out of spec.
With an ability to support nearly any serial interface up to 6.25 Gbit/s (including TFI-5), these cores should find a warm welcome in HBAs, storage controllers, serial disk drives Ethernet routers, backplane switches. Agere says that they will make its debut in some of their standard products, Serial RapidIO, SAS and SATA interfaces, and read channel controllers early in 2005. They have several ASIC projects slated to be released later, in the new year.
Agere's SerDes core technologies are available now for ASIC macro cell integration.
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