CEVA Inc. has announced the CEVA-TeakLite-III, a third-generation DSP architecture based on the broadly adopted TeakLite family of DSP cores. This feature-rich native 32-bit architecture is backward compatible with previous versions of CEVA-TeakLite cores and delivers higher performance and lower power for demanding applications such as 3G cellular handsets, High Definition (HD) audio, Voice-over-IP (VoIP) and portable audio devices.

 

For the first time, a DSP compatible with the CEVA-TeakLite architecture delivers native 32-bit processing, which includes a 32 x 32 MAC unit to provide efficient support of advanced audio standards such as Dolby Digital Plus 7.1, Dolby TrueHD, DTS-HD and more. The architecture also features a 10-stage pipeline, enabling the core to reach operating speeds of up to 425MHz in a 65nm process (worst-case conditions and process). Compared to CEVA-TeakLite, initial performance estimates show it to be up to 4 times faster on basic operations and 2 times better on most popular audio codecs.

 

“High-volume applications such as HD audio and multi-mode handsets require a DSP engine offering substantial performance, at low power consumption and smallest die size,” said Gideon Wertheizer, CEO of CEVA. “Both new customers and the large install base of licensees with CEVA-TeakLite legacy software investment will benefit from the performance and features that CEVA-TeakLite-III offers to extend the capabilities and market reach of their next generation products.”

CEVA-TeakLite-III builds on the architecture of CEVA-TeakLite-II, CEVA-TeakLite, and CEVA-Oak, the most established and successful licensable DSP architecture to date. The CEVA-TeakLite family has been licensed to over 50 partners worldwide and has shipped in over 750 million devices. CEVA-TeakLite-III is fully compatible to CEVA-TeakLite and CEVA-Oak architectures, allowing its users to leverage both existing applications and the large software installed base already available from CEVA and the CEVAnet third-party development community.

 

The flexible CEVA-TeakLite-III architecture is available in various configurations, each specifically tailored for particular applications and system architectures. CEVA-TL3210 and CEVA-TL3214 are two specific configurations of the architecture, available for licensing today. CEVA-TL3210 includes a mix of tightly coupled memories and direct mapped caches, and allows easy SoC integration using AHB bus protocols. CEVA-TL3214 targets cost sensitive SoCs based on a TeakLite-compatible X/Y data structure and minimizes SoC integration investments. An additional configuration, the CEVA-TL3211, includes an advanced 2-level cached memory subsystem equipped with a memory protection unit and AXI system interfaces. This configuration targets single-core embedded applications and will be available for licensing in early 2008.

 

Targeting next-generation Hi-Fi audio applications, the CEVA-TeakLite-III inherently supports 32-bit data processing functions with multiple precision points and offers an enlarged 64-bit data memory bandwidth. An FFT accelerator further boosts audio performance and reduces power consumption. For example, a 7.1 channel Dolby Digital Plus decoder would consume only 15% of the core’s available MHz at a 90nm process, compared to 47% for its predecessor, the CEVA-TeakLite.

 

3G multimode and portable audio applications are enhanced through dual 16-bit multipliers, a built-in Viterbi accelerator and a set of SIMD and parallel instructions. By utilizing a 10-stage pipeline, the CEVA-TeakLite-III runs at 350MHz in a 90nm G process, and up to 425MHz in a 65nm G process, using the worst-case corner.

 

The new CEVA-TeakLite-III DSP architecture embeds CEVA’s patented CEVA-Quark instruction set, a comprehensive stand-alone 16-bit ISA that allows customers to develop complete applications for cost-sensitive markets. Moreover, customers can seamlessly mix CEVA-Quark instructions with more advanced instructions without the need for mode switching. This enables better code density for CEVA-TeakLite-III based designs and requires less memory, die size and power as a result.

 

With next-generation wireless and digital media devices requiring larger program size, increased local frame buffers and efficient multi-tasking, CEVA-TeakLite-III expands its predecessor’s memory addressable space by offering a 4 GB address space for code and data memory. The core also offers a 32-bit unified general purpose register bank and a 32-bit integer unit, with bit manipulation and quick look-up-table access capabilities, as well as a branch prediction mechanism, to further enhance its micro-controller feature set.

 

CEVA-TeakLite-III is a fully synthesizable soft core and a process-independent design that allows licensees to specify the silicon area, power consumption and speed that best suits their needs.

 

As with all CEVA solutions, CEVA-TeakLite-III is supported by a robust development environment that includes a highly efficient C/C++ compiler, an advanced GUI debugger, a built-in instruction set and cycle accurate simulators, a complete set of binary tools, and a profiler to measure performance. The development tools run on Windows, Solaris and Linux, and are supported by a worldwide customer service team. CEVA-TeakLite-III is further complemented by extensive algorithms and applications from CEVA and the CEVAnet third-party development community.

 

 

 

Although completely code-compatible with their earlier TeakLite-II core, CEVA’s TeakLite-III core is a significant upgrade in terms of performance and flexibility. Moving from the II’s 16-bit bit architecture to 32 bits adds the necessary for precision audio while an enhanced instruction set makes it much easier to run tasks traditionally supported by a separate RISC controller, such as protocol stacks and MMIs. Add to this several specialized processing and a longer pipeline (now 10 stages) and you have the ingredients for a processor that should meet the demands of most handheld multimedia applications.

 

The new 32-bit architecture features a 32x32 scaled multiplier that gives single-cycle 64-bit results and performs 2-cycle butterfly operations to speed up FFTs and other compute-intensive operations (see Fig. 1). The CEVA press release above paints a fairly accurate picture of the rest of the processor architecture, but I’d like to highlight some of the interesting architectural details that allowed them to create a powerful 32-bit capable core that’s both code- and silicon-efficient.

 

Much of the efficiency is a result of CEVA’s new Quark instruction set and decoder that accommodates both 16- and 32-bit instructions. Most critical instructions are 16-bit, allowing for smaller memory footprint and 16-bit instruction memory. In this way, CEVA made sure that the architecture allows mixing of 16 and 32-bit instructions without invoking a special mode or wasting cycles. The Lite-III segmented, dual MAC processing logic works within the Quark instruction set to perform up to three parallel instructions per clock cycle while keeping instruction set within the 32 bit limit. CEVA has also added audio-specific instructions specifically designed to save lots of instructions when running code for advanced audio codecs -- including the latest Dolby algorithms.

 

As the release notes, the Lite III has a bunch of RISC-like features including a 4 Gbyte memory space, a cached memory subsystem, and memory management/protect logic that should make developing solid multi-tasking applications much easier. A 32-bit integer math unit allows single-cycle calculations for many non-DSP operations. All these features deliver enough power that should help this core absorb controller functions in many applications.

 

The Teak Lite-III precision audio features should make it a good choice for providing advanced audio processing in receivers, HD-DVDs, STBs and other HD home entertainment products. Its ability to handle both baseband audio processing and controller tasks will help designers control cost and power consumption in price-conscious 2G/2.5G/3G handsets as well as personal media players. I also agree with CEVA that its raw DSP power could find it warmly welcomed in VoIP gateways where a single core can support up to 10 IP voice channels, including echo cancellation, DTMF, voice codec and support of networking protocol stacks.

 

CEVA-TL3210and CEVA-TL3214 are two specific configurations of the CEVA-TeakLite-III architecture that are available for licensing today. The CEVA-TL3211 will be available for licensing in early 2008.