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dspZONE Products for the week of November 3, 2008
Freescale Semiconductor Says…
DSP Sets New Performance Standards To Speed Deployment of LTE and Other Next-Generation Wireless Standards
New six-core MSC8156 delivers 6 GHz performance; integrates enhanced StarCore technology and multi-standard accelerators at 45-nm geometries for a cost effective solution
Freescale Semiconductor has introduced the MSC8156 processor − a six-core device based on new SC3850 StarCore DSP core technology and designed to dramatically advance the capabilities of wireless broadband base station equipment.
The MSC8156 is one of industry’s first infrastructure DSPs based on 45-nm process technology, endowing the part with performance, energy efficiency and form factor advantages. It delivers the flexibility, integration and affordability required for mainstream, near-term deployment of networks based on LTE and other next-generation wireless standards.
The MSC8156 delivers twice the performance and consumes half the power as Freescale’s MSC8144 device, which was previously the industry’s highest performing programmable DSP. Providing five times greater spectral efficiency than many advanced HSPA networks, the MSC8156 enables optimal economics for operators and opens the door to entirely new categories of end-user services.
“The MSC8156 DSP offers OEMs and telecom carriers the performance they need to bring LTE and other next-generation wireless services to life,” said Dr. Lisa Su, senior vice president and general manager of Freescale’s Networking & Multimedia Group. “Our ongoing investment in StarCore technology continues to pay dividends for Freescale, our customers, and ultimately the millions of consumers looking forward to richer, seamless and more compelling wireless experiences.”
A single chip that replaces discrete parts required by competing solutions, the MSC8156 DSP’s exceptional performance supports the high throughput and low latency requirements of next generation base stations and high data rates attained by the latest OFDMA standards. Additionally, its onboard multi-standard accelerator technology gives OEMs the flexibility to create affordable LTE base stations while extending their existing WiMAX, HSPA and TD-SCDMA designs. Using the device, OEMs can maintain the same flexibility as a DSP-plus-FPGA solution—at lower cost and without the expense associated with specific adaptation of non-standard products.
Acceleration technology for performance and flexibility
The MSC8156 integrates Freescale’s high-throughput Multi Accelerator Platform Engine technology for baseband (MAPLE-B) acceleration to deliver outstanding flexibility and performance. MAPLE-B contains two configurable RISC engines, which can be reprogrammed in the future to accommodate updates.
The six fully-programmable DSP cores work with the MAPLE-B accelerator to support the 3G-LTE, TDD-LTE, TD-SCDMA, and WiMAX standards, as well as the symbol rate functionality of HSPA and HSPA+. Delivering multi-standard capabilities on a single platform eliminates the need to redesign hardware for different base-station standards, so the device is scalable across macro-, micro- and pico-base station form factors.
Additionally, MAPLE-B helps the MSC8156 deliver the performance to process the PHY functionality of a single sector of 3G-LTE 10MHz with data rates of up to 144Mbps at the downlink path and 72Mbps at the uplink path with 4x4 MiMO.
Introducing StarCore SC3850 core technology
Freescale’s new StarCore SC3850 DSP core and subsystem are a binary-compatible evolution of SC3400 StarCore DSP technology. Key enhancements to the previous generation include a 2X increase in DSP multiplication capacity, significantly higher compiled code performance and an improved memory hierarchy.
SC3850 technology is the first new generation of StarCore DSP cores since Freescale internalized the StarCore architecture in 2006. The new cores are capable of performing eight 16x16 MAC operations per cycle, enabling performance of 8 GMACS for each of the device’s six cores. The SC3850 subsystem also includes a unified, private, low latency L2 cache that significantly improves application performance. With the addition of smart pre-fetching mechanisms, the L2 cache also simplifies the software architecture by eliminating the need to base the application on direct memory access (DMA) technology.
The SC3850 is fully backward binary compatible with previous StarCore architectures. Micro-architectural improvements and new instructions enable the core to accelerate control functions, memory management, and DSP code performance.
Among the legacy features of the SC3400 retained and enhanced in the SC3850 are a fully featured MMU with robust task protection, address translation and memory attribute management.
MSC8156 technical details
Fabricated in 45-nm process technology, the MSC8156 DSP features 4 Mbyte of embedded memory, enhanced memory hierarchy and cache performance for efficient processing, a configurable L2 cache or M2 memory at size of 512Kbyte attached to each of the six cores and 1Mbyte of shared memory. It supports dual 64-bit double data rate (DDR3) external memories at up to 800 MHz and a variety of high speed interfaces including dual Serial RapidIO x4 ports, PCI-express x4 port and Dual 1G Ethernet (SGMII). The MSC8156E also integrates security accelerator with supports for AES, SNOW-3G, 3DES/DES and Kasumi algorithms to accelerate the MAC functions.
Development tools and software
Freescale offers a full set of development tools and enablement software for the MSC8156 device. The Eclipse-based CodeWarrior Integrated Development Environment (IDE) from Freescale is a highly comprehensive multicore development environment. It includes: C & C++ optimizing compilers, source level debugger, profiler, linker and royalty-free SmartDSP-OS operating system delivered with optimized device drivers. Development boards are available to enable software development along with a set of reference optimized software components for 3G-LTE.
EN-Genius Says…
Unlike TI, which only recently embraced multi-core DSPs instead of simply bumping clock speed and the number of MACs/cycles to deliver more processing power, Freescale has been building multi-core devices for quite some time. In fact, their early StarCore products offered various combinations of PowerPC and DSP cores as far back as somewhere around 2001. Back then (when they were still known as Motorola), they solved the problems that plagued many first-wave multi-core designs whose inter-processor connections and I/O were prone to blockage and resource conflicts. Motorola’s early devices solved the problem with a powerful switched interconnect architecture whose genetic code can still be seen in the MSC8156 6-core DSP they’ve announced here. That legacy is evident as the advanced interconnect system allows the MSC8156 processors and their associated hardware accelerator cores to work smoothly together to deliver a cost- and power-efficient solution to demanding 3G wireless applications.
The MSC8156 features six of their SC3850 StarCore series DSP cores coupled to a crypto accelerator, a powerful hardware baseband processor core (more about this later), and a powerful set of I/O and two high-speed memory interfaces. While code-compatible with earlier SC3400 DSP cores, the new processors deliver up to 8 MACs per op cycle (versus four MACs/cycle in prior generations). The processor architectural mods also include several new native instructions that should cut the number of clock cycles required to perform the FFT/IFFT operations that are so commonly used in wireless baseband applications. Each core has its own L1 (32 k) & L2 (512 k) cache plus 1 M of shared memory that uses a semaphore mechanism to coordinate read/write ops. The six processors communicate with each other via an upgraded version of the non-blocking switch fabric used in all StarCore multiprocessor chips. The fabric provides each core with two independent links to allow for simultaneous multiple operations (eg performing a DMA operation while working with the crypto accelerator or other peripheral). The processors use the same interconnect fabric to share a pair of flexible 64-bit 400-MHz DDR2/3 memory interfaces.
There are several other subtle but important tweaks to the internal DSP cores micro-architecture that give them improved control code performance (for better parallel condition computation) and improved branch prediction that enables better cache efficiency and higher success rates for speculative executions. Code efficiency is further improved thanks to the new pre-fetch memory transfer feature that moves blocks of data faster than traditional DMA because its single command execution eliminates most of the set-up and overhead steps you’d normally have to do to set up a memory transfer. Although the new DSPs are binary code-compatible to allow you to run legacy software without tears, Freescale does recommend that, wherever possible, you recompile your code to take advantage of all the new features.
 The other clever bit Freescale has added to the mix is the MAPLE-B–Baseband Accelerator core. It was originally offered as stand-alone chip (the MSBA8100) this Spring and handles nearly any standard baseband processing operation in hardware, freeing up the DSPs for more important work. I got a brief tour of the core architecture and found it to be very impressive but, unfortunately, was not permitted to reveal any details or publish the architectural block diagram that I saw. All I can say is that you should be able to count on the MAPLE-B core to offload the compute-intensive elements of most commonly-used wireless algorithms including Turbo/Viterbi encode/decode (up to 200/115 Mbit/s), Fourier Transform (up to 280 Msample/s), FFT (175 Msample/s) and DFT for the: 3G-LTE, 802.16, 3G, CDMA2K standards. This heady mix of fixed-function and general-purpose computing is a great way to reduce the cost of advanced wireless equipment to serve the 3G-LTE, TDD-LTE, WiMAX, HSPA+ and TD-SCDMA•markets. A single chip can form the heart of a small 3G-LTE or WiMAX base station.
It’s relatively easy to gang multiple processors together via the dual 4-lane Serial RIO ports to build larger, multi-sector systems. A three-sector, 20 MHz MIMO LTE base station requires only three MSC8156 devices. It can even be used to build multi-sector HSPA equipment although the processors require external chip rate acceleration (typically done with an FPGA). In case you’re considering using a PCI Express-based host system, fear not, Freescale gives you the option of a 4-lane PCIe connection as well.
As with any new IC that’s this complex I have concerns about whether the MSC8156 would work as advertised and not have problems with yield. Back when 90-nm processes were still very new, there was at least one large Freescale processor (and several other parts from other vendors) that were in painfully short supply until the design could be adjusted to be more tolerant of process variations. Freescale says that they’ve worked closely with their 45-nm fab, using test runs of selected design elements to verify yield at corner case conditions. I was also encouraged to learn that Freescale verified the entire design in both software and a FPGA-based test rig before committing to silicon. Between the extra precautions they’ve taken and the fact that many of the individual elements that went into this new DSP have already been implemented in other commercial products, I’m relatively confident that Freescale will have working devices somewhere close to their Q1 2009 goal. I am also relatively confident that power consumption for production versions of the MSC8156 will be something close to the 10 W estimates I was given (I did not find out whether this was for the 800 MHz or 1GHz version).
If Freescale has correctly identified the need for a high-capacity DSP that’s been specially tweaked for 3G wireless applications, the raw processing power and low solution cost that this new multi-core monster brings to the game should win them a fair share of business in the next generation, or two, for wireless infrastructure equipment.
Freescale plans to sample the MSC8156 to alpha customers during Q1 of 2009. It is offered in an FC-PBGA-783. The company plans to offer the device in two versions, based on core speeds of 800 MHz and 1 GHz. Pricing starts at $192 for 10 k volumes.
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