Greetings from Santa Clara, the city that’s the home of
DesignCon, a favorite annual gathering for electronics engineers who surf the cutting edge, and is only a stone’s throw from San José’s (in)famous
Fourth Street Bowl, a favorite late-night hang-out of certain high-tech journalists. As with most recent DesignCons, the
program provided a SPICE-y mix of digital and analog topics aimed at pushing electrons around chips, boards, cables and other media at unreasonable speeds, typically in excess of 10 GHz. Given the eclectic mix of topics that appears at these events, it’s often hard to find any single focus, but this was not the case this year as solutions to the predicted Internet bandwidth shortage seemed to dominate so many of the sessions.
If we are to believe the dire predictions made in Loring Wirbel’s
Understanding the Impact of 100G Ethernet panel
session are true, we can expect the Internet to grind to a crawl in a couple of years if the siliconistas cannot deliver a commercially-viable 100 Gbit/s technology. While it’s likely that the cries of imminent doom and disaster being made by reps from Sprint, Cox, Netflix and other bandwidth-intensive enterprises were a bit overstated, it’s pretty obvious that, barring a complete economic meltdown, the demand for fast bits will outstrip the supply sooner than later. Now the big question in my mind is whether the bottleneck will show up first in the networking technologies as they struggle to deliver a workable 100 Gbit/s standard or whether the backplanes that feed them won’t be able to make the next speed jump in time.
From where I sit, backplanes and other chip-to-chip connections are the likely pinch point since even the 10 Gbit/s connections that are starting to become commonplace are quickly overwhelming even the fastest commercial interconnects that we have today. I’m just hoping that it won’t take too long for the chip makers, connector makers, and the folks who make the printed circuit boards to sort out who’s going to shoulder which part of the burden for improving the channel enough to make a cost-effective 25 Gbit/s serial link that won’t turn the chassis it sits inside into a toaster. Unfortunately, what I’ve seen indicates it will be at least 18 months to two years before we see anything available to mainstream designers.
Some of the obstacles to a decent 25 Gbit/s SerDes link became apparent in the DesignCon
panel I chaired
(The Call for Industry Research on Next-Generation Electrical Signaling) was at once hopeful and alarming. The good news is that the technology to support 25 Gbit/s in a backplane environment can be realized. The bad news is that we’re still trying to untangle the messy relationship between striking a balance between backplane cost and silicon complexity. Interestingly, several papers I saw at DesignCon indicate that, with proper back-drilling (to eliminate via stubs) and a bit of attention to how the signals are routed to their connectors, FR4 backplanes can probably be coaxed to support data rates of well over 25 Gbit/s, with not too much more equalization, cancellation, and error correction than can be crammed into an affordable chip using 65-nm processes. The big challenge is coming up with some way to define a set of channel characteristics that transceiver makers can work with but don’t impose unacceptable costs on backplane makers.
At first glance, it would seem to be a relatively simple task to nail down a common set of parameters that both sides could work towards but it seems that there may be a hidden, unstated market factor that’s slowing down this convergence. I did not understand the problem myself until a reliable source pointed out that the unstated rule for any of these technologies is that they be able to drive a handful of worst-case channels in the legacy backplanes of a couple of extremely popular enterprise router product lines made by a certain large networking equipment manufacturer. Without the ability to upgrade the capacity of even the oldest units in the series, the possibility of sales to the industry’s largest potential customer would be close to zero, something that would leave a large hole in even the most optimistic chip maker’s business plan. I’m not sure if this scenario is really influencing the development of a next-gen backplane standard, but it could certainly at least partly explain why it’s taking so long to converge on a set of requirements everyone can agree to live with.
Comments? Questions? Speculations of what’s really going on with the five undersea cables that have been mysteriously
severed in the past few weeks? Write me at
lhg at en-genius dot net, or post your comment on our blog.
