Given the rapidity of advancing technology, especially the incredible gate counts of today's ASICs and FPGAs, it's a wonder working engineers can keep up (that's where EN-Genius.net helps). I thought of this recently when performing some CMOS logic troubleshooting.
The circuitry I encountered was very outdated, but it worked, faithfully fulfilling the application requirements it was originally designed for. A large packaging panel housed a number of logic daughterboards. One such board was built with lots of 4000 Series and 7400 Series TTL logic. These ICs converted analog discriminator outputs into logic levels that were ultimately used to drive process control loops and indicators.
Out To Pasture?
Now, lest you laugh at what most certainly was antiquated electronics, remember this: the customer was happy with the system's reliable operation, and had used it successfully for nearly ten years. A number of these boards were in place and operating daily, so his organization only had long range plans for updating or modernizing this control circuitry. No matter how obsolete it was, it filled the proverbial bill. The system wasn’t quite ready to be put out to pasture.
What was vexing was that the system logic would work for days on end and, then, mysteriously fail, only to start working again after a half hour or so. Naturally, I checked power supply rails for proper voltages and noise, and rigorously cleaned, poked and tweaked the system's numerous separable interconnects for mechanical faults and intermittents. Temperature was considered, but the packaging panel was adequately cooled and the fan's filters were periodically cleaned. As you might expect, no faults could be provoked, the system ran cool, and voltages were not amiss.
With the various devices socketed in high-reliability screw machine sockets, it was relatively easy to swap ICs (try that in an ASIC). I did this reluctantly, knowing that ICs are very reliable, especially after being burned-in for nearly a decade. Nonetheless, when the problem reared its head, probing with a scope revealed errant data at a number of points.
One of these points was a quad 2-input NAND gate. For those of you brought up on the language of CMOS glue logic, it was a 4011 DIP-14. Only two of the quad device's gates were used.
While probing the device, I noticed that one of the two unused gates wasn't terminated. Whoever designed the board simply overlooked it, or perhaps the technicians or assembly workers went out to lunch early that Friday.
Terminate Those Unused Inputs!
Now, it was considered good engineering practice back in the mid-1980s to terminate all unused CMOS inputs, to either the positive supply rail or ground, and the designer of this board did that on all of the devices – except one gate on this errant 4011. Could this be the culprit?
I had heard of CMOS packages operating with power source pins unconnected (in these cases, the chip apparently derives operating power through gate input-protection diodes). I also knew about substrate latch-up. In the back corners of my memory I recalled reading about unused inputs on CMOS exhibiting long time-constant charging characteristics, resulting in erratic operation, including adjacent gates.
So, with soldering pencil in hand I carefully added a bit of wire (no CAE here) to the two input pins of the unused 4011 gate. That was it. Problem solved. The circuitry never got balky again.
But, why would such a problem wait nearly a decade to rear its head? Were there long-term wear-out mechanisms in play? Cosmic radiation? Or was this antediluvian circuitry simply obeying Murphy's Law ("If anything can go wrong, it will") ?
Your comments are welcome. Please write me at amm at en-genius dot net, or post your thoughts and observations on our blog.
