Reducing System Power With A New NAND Flash Memory Interface
by Peter Gillingham, Vice President and Chief Technology Officer, MOSAID Technologies Inc.
Power consumption in NAND Flash memory subsystems, particularly those with large numbers of memory devices such as SSDs (Solid State Drives), is typically dominated by the I/O power dissipated in transferring data between the controller and the memory devices. Achieving low power is an important consideration. In mobile devices, such as cell phones and media players, extended battery life or smaller form factors can be achieved with reduced power mass storage devices. In enterprise applications such as SSD storage arrays, low power NAND devices provide a reduced thermal budget which leads to higher computational density and reduced energy costs.
A new ring topology that delivers significant power benefits over the traditional bus topology can be employed by all mainstream memory devices, including NAND Flash, NOR Flash, SRAM and DRAM. An SSD implemented with this architecture can use half the power of an equivalent SSD employing an ONFI (Open NAND Flash Interface), 2.0 NAND Flash device. This is significant in both portable applications where battery life is critical and in enterprise applications where heat and energy footprint considerations dominate.
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