|
 |
networkZONE Products for the week of August 4, 2008
Teranetics Says…
Industry’s First Dual-Port 10 Gigabit Copper PHY
Company extends 10GBASE-T leadership with a solution that delivers switch port-density required for mass adoption of 10 Gigabit Ethernet
Teranetics, Inc. has introduced the industry’s first dual-port 10GBASE-T PHY IC. A second generation PHY, the TN2022 doubles the port density of switch and Network Interface Cards (NIC) compared to first generation 10GBASE-T PHYs. With the smallest form factor available and low power profile, the TN2022 enables switch manufacturers to design as many as 48 RJ-45 ports into a single rack unit.
Typically, 48 ports is the highest density available for stand-alone 1 Gigabit Ethernet switches in one rack unit. Because the TN2022 supports development of new 10 Gigabit products with the same port count, original equipment manufacturers (OEMs) can now design systems that deliver 10 times more bandwidth at nearly one-third the cost per Gigabit of bandwidth. At this density and price level, 10 Gigabit Ethernet becomes an attractive choice for data center managers who require bandwidth upgrades in addition to a fabric for unifying multiple networks in the data center.
“Teranetics is once again in the lead among 10GBASE-T PHYs,” said Jag Bolaria, Senior Analyst, Linley Group. “The small footprint of the dual-port PHY eases system design and yields port density needed for lower cost per port.”
“By looking at the underlying needs of OEMs and their data center customers, Teranetics continues to design technology that encourages mass adoption of 10 Gigabit Ethernet,” said Kamal Dalmia, vice president of Marketing at Teranetics. “With this new generation product, our OEM customers can fulfill the data center manager’s desire to use RJ-45 for the vast majority of 10G connections in the data center using their current wiring and infrastructure.”
Teranetics established itself as a leader in this market, by developing the smallest form factor first generation 10GBASE-T PHY. This product has been adopted by leading OEMs, such as Extreme Networks, Inc. and Mellanox Corporation. Now, the TN2022 extends the company’s market leadership and sets a new bar for the industry. This second generation PHY consumes 6 watts per port and nearly halves the power consumption compared to first generation PHYs while operating at cable lengths exceeding 100 meters. In addition, the TN2022 features multi-rate capabilities, enabling use with ubiquitous RJ-45 Ethernet connectors and making it backward compatible with existing 1 Gigabit and 100 Megabit network gear.
“As a leading provider of 10G switches to the enterprise and service provider segments, Extreme understands that switch density and power consumption are critical to the development of attractive solutions,” said Douglas Murray, vice president and general manager at Extreme Networks. “The Teranetics TN2022 advances the technology while establishing a strong foundation for 10GBASE-T architectures.”
EN-Genius Says…
From the published specs of Teranetics 2nd-generation dual-port 10GbE PHY, it seems to be well-equipped to help move 10GbE from trials to mass deployment. At 6 W/channel, it draws only a little more power than the earlier 10 W single-port PHY, and manages to squeeze two ports' worth of 10G Ethernet into the same 25mm x 25mm die that its predecessor used. Teranetics was pretty tight-lipped on the details of both their transceiver architecture and how they managed to shoehorn two of them onto a relatively small die, but I was able to learn a few things about the its design that may shed a bit of light on the transceiver's inner workings and how well this promising device will live up to its claims.
Both the single- and dual-port transceivers use feed-forward equalizers (FFEs) to help their receivers cope with the extremely nonlinear attenuation that multi-Gigabit signals experience in most cables and PC traces. Inter-symbol interference (ISI) is handled by a 1000-tap echo canceller while a LDPC decoder provides 10 dB of coding gain. Teranetics says that some of its most prized IP lies in its decoder which uses a fine-tuned mix of pipeline, parallelism and folding techniques to meet the stringent 2.5 µs latency requirement in the 10GBASE-T spec.
 This intelligent receiver architecture also makes it possible for the TN2022 to support some very sophisticated diagnostic capabilities including a per-line TDR probe that can precisely locate impedance discontinuities (line kinks, line breaks, and partial shorts) in a cable or PCB trace. Teranetics also offers so-called scope-on-chip software that allows a standard PC to control the receiver’s slicer circuits via its MDIO port and deliver a digitized image of the data eye that the chip is actually seeing.
A good portion of the TN2022 energy and silicon savings is attributable to its move from a 130-nm to a 65-nm process, but Teranetics says that they also made some architectural changes that helped keep the transceiver power consumption low. While Teranetics was unwilling to give even a hint about what changes they made to help cut power beyond what the move to 65 nm was able to deliver, I’ll speculate that it was a combination of more efficient implementations of some of the digital filters on the front end, perhaps eliminating some unnecessary filter/equalizer functions. I’d also guess that they were able to use the experience gained with their first-generation transceiver to selectively reduce some of the margins in the analog elements.
Like its predecessor, the TN2022 employs many of the energy management tricks that other manufacturers use to help to keep its power consumption well below the 6 W/channel maximum in all but the most difficult channel environments. Most of these power savings come from the receiver’s ability to dynamically adjust how much of its equalization, a NEXT/FEXT cancellation, and echo cancellation circuitry it actually uses according to the attenuation and other channel impairments it sees. Teranetics says that this will allow the TN2022 to dissipate much less than its maximum 6 W when driving the shorter 20 - 30m cable lengths typically used in most data centers.
In addition to the power and cost advantages it enjoys, the TN2022 adds a three-speed auto-negotiation feature that is a significant improvement on the dual-speed capabilities of the first-generation parts. It uses separate DSP coding elements for the 10G and 1G/100M coding which are channeled to a common AFE. By supporting all Ethernet speeds down to 100 Mbit/s, designers can deliver routers, servers, and other boxes that will support legacy equipment within a data center and not require forklift upgrades at the desktop – a critical feature for mass deployment of 10G. For the record, Aquantia’s second-generation (single-port) device that’s scheduled for release later this year will also feature triple-speed capabilities as well as power consumption that matches, or does a bit better, than the Teranetics part (Aquantia’s single-port, single-speed AQ1001 alpha silicon was reviewed here in April 2008). Both devices also use innovative front-end designs that eliminate the need for external hybrid circuits to tie together the transmit and receive circuits. It is unclear, however, whether Aquantia (or SolarFlare) will be releasing their own dual-port chips any time soon.
While we’re on the subject of Aquantia, there are strong rumors of a single-chip MAC/PHY under development there. If the rumors are true, it could give them an advantage as the10GBASE-T market heads towards commodity status over the next 18 - 24 months.
As one would expect, Teranetics makes some very good counterpoints about the advantages it still enjoys over Aquantia. For one thing, they point out several architectural differences that they feel set them apart from Aquantia. These include the DSP algorithms used in the echo and crosstalk cancellation, which they feel enable the PHY to do a better job at canceling the heavy crosstalk that occurs in RJ-45 connectors and is often worse when manufacturers cut corners in materials and dimensional tolerances. They also claim that their EMI suppression (most critical for XFI apps) was designed with extra margin to ensure shipped products don’t encounter problems.
Teranetics also says that they’ve had a year’s lead on encountering and overcoming several subtle real-world problems that were not apparent until their chips were in the field for a while. For example, although their PHYs were completely compliant with the 10GbE standard, nobody thought of the fact that the receiver might have to cope with rapid variations in channel characteristics that occur in real time on long cable runs as cables are shaken or moved during plant maintenance. Apparently, the control loops in the first silicon were slightly too slow (a power-saving measure) and the PHYs would drop out when the cables they were driving were jostled too much. Teranetics solved the problem by tweaking receiver control loops so they compensated quickly enough to keep the link alive without burning too much extra power. In light of this and other incidents, they say that, regardless of how brilliant a silicon company’s designers are, there are several other little hidden gremlins like this that they’ve already overcome and that Aquantia, and any other would-be competitor, will only encounter when they field their first silicon.
One concern that I have about the upcoming 10GbE PHYs from all the manufacturers is that their complexity and their reliance on standard CMOS processes to support extremely high-performance analog elements could make them susceptible to yield problems. As with other chip makers, Teranetics was unwilling to give me any details that would address this, other than to say that their engineering staff includes several seasoned analog designers who have included lots of margin in the chip’s critical elements to help ensure that processes don’t affect yield.
The TN2022 dual-port 10GBASE-T PHY transceiver is now available in sample quantities priced at under $100/port.
|
|
|
|
|
