networkZONE Products for the week of October 15, 2007
TPACK Says…
TPWX3192 Combines Packet Mapping And Switching
TPACK has announced the availability of a groundbreaking new solution, the TPWX3192 Carrier Packet Mapper Engine. Combining the functionality of a 10 Gbit/s Ethernet over NG-SONET/SDH packet mapper and a carrier grade packet processor with traffic management, the TPWX3192 is ideal for cost-optimized MSPP and microMSPP as well as packet optical applications.
The TPWX3192 is the first TPACK product to take advantage of the high logic density and low power consumption of Altera’s new line of Stratix III FPGAs. Based on 65nm manufacturing processes, the Stratix III FPGAs enable the TPWX3192 to accommodate the feature sets of both the TPACK TPX3100 20Gbit/s Carrier Packet Engine and the TPACK TPW192-S 10 Gbit/s NG-SONET/SDH Packet Mapper. This allows the full range of MEF defined Carrier Ethernet Services to be supported in a compact, single device solution.
“By combining two products in one, the TPWX3192 provides a lower cost solution, occupying less space and consuming 50 percent less power without sacrificing features or flexibility”, said Peter Viereck, CEO TPACK. “With the 10x increase in bandwidth required by triple-play and IPTV services, the TPWX3192 allows affordable 10 Gbit/s NG-SONET/SDH aggregation solutions to be deployed that can extend the capacity of existing networks.”
“TPACK is taking advantage of the best-in-class performance and low power consumption of the Stratix III FPGA in the TPWX3192 to deliver a highly-integrated, complex Ethernet solution,” said David Greenfield, senior director of product marketing for high-end FPGAs at Altera Corporation.
EN-Genius Says…
If I’d known about TPACK back in July (2007), I might not have written the Editorial that bemoaned the recent lack of innovation in SONET/SDH semiconductors (see Paving Paradise). Actually, the highly-configurable FPGA-based device that combines a 10 Gbit/s SONET/SDH mapper and a powerful Ethernet switch is almost precisely what my Editorial predicted to be the logical successors to the ASICs that major telecom vendors have traditionally relied on to implement custom functions and feature sets. Surprisingly, the TPWX3192 should also provide a more flexible alternative to the fixed-function merchant ASSPs that smaller vendors have used in their designs. The processor’s collection of packet inspection, processing and encapsulation features is so extensive I won’t even try to list a portion of them here. See their product brief for the complete can of alphabet soup.
 As the release above notes, the TPWX3192 is actually the integration of two existing IP cores -- their TPW192-S Ethernet over SONET, GPP/VCAT/CCAT/LCAS-capable mapper/framer and the TPX3100 full-duplex L-2 Ethernet switch/packet processor. Packet processing and lookup is handled by a single-stage processor that uses the same number of clock cycles on each packet in a manner that’s vaguely reminiscent of Xelerated’s pipeline packet engine (although TPACK states firmly that it is not a pipeline). Its deterministic behavior allows it to support carrier-grade features like 50 ms protect switching, guaranteeing 3.3 ms intervals between OAM packets, and other time-sensitive SONET/SDH performance requirements.
 The switch element is a shared-memory fabric that switch handles both TDM and packet traffic, TPACK has designed it so its capacity can be divided up across SONET/SDH cross-connect elements (up to 64 k) and VLAN/MAC IP switches (up to 8 k).
It can slice and dice the traffic from its two 10 Gbit/s feeds into 256 logical ports with 72 k flows (64 k Ethernet/VLAN flows, 8 k MPLS flows). Traffic management can be programmed with up 8 queues per port using any one of several queuing schemes including strict priority, RR, and WRR.
 At the heart of the switch element (and many of the chip’s other functional blocks) is a pointer manipulator that uses commercial QDR II RAM as its buffer. The buffers in other parts of the chip are a patchwork of QDR, RLD and DDR (a legacy from the earlier core that the device is built from) but TPACK has hinted strongly at plans to optimize on a single memory type in future designs. But even if the current mapper/switch needs a few chunks of more expensive memory to do its job, its RAM-based hash lookup logic does manage to eliminate the need for even more costly, power-hungry TCAMs.
This tightly-coupled mapper/processor/switch can efficiently move 10 Gbit worth of traffic between the packet and frame domains using either existing conventional VCAT/LCAS EoS technique or the relatively new provider backbone transport (PBT) protocol. This PBT capability could become a major selling point for the TPWX3192 as carriers begin to appreciate its advantages. In a nutshell, the protocol removes the SONET/SDH overhead from the TDM stream to transport Ethernet in a connection-oriented manner with more granularity than conventional VCAT/LCAS EoS techniques while giving it carrier-class manageability and reliability.
The design flexibility and rapid development that TPACK FPGA-based products deliver should be welcomed with open arms as an alternative to ASICs by carrier equipment makers who must meet stringent performance and interoperability standards, but still differentiate themselves with advanced, proprietary features. One area where the advantages of a configurable chip are most easily seen is in the network interface. Each of the TPWX3192 10G connections can be configured as a series of 10/100/100 RGMIIs, a 10 XGMII or a SPI 4.1 interface to provide whatever mix your application needs. The code that configures the packet processing engine and switch fabric is also designed to accommodate custom features and functions, such as proprietary overhead processing or hooks to work with existing ASICs.
Combining the mapper, packet engine and switch functions on a single FPGA was made possible in equal parts by the high logic density of Altera Stratix III family and TPACK’s careful design of their own IP blocks that use up to 50% less fewer logic elements than the equivalent functions in Altera’s development tools. Together, they also drop the power consumption from 40 W for the two-chip set to 22 W.
Even with all this economizing, the TPWX3192 is still a formidable design that requires a 340K LE device, close to the top of Stratix’s size range. Most applications can be pared down to a smaller, less expensive FPGA by deleting unneeded features. TPACK says that frequently this means eliminating lower-order channels in GbE applications don’t require finer granularity, or unneeded overhead processing functions.
Thanks to their willingness to clarify some thorny technical issues and a respectable track record, TPACK scores quite well on the Vapor Index Rating. Although TPACK is relatively new to merchant silicon, they have a longer history as an IP company whose images, drivers, and support software is running in the bowels of high-end carrier equipment sold by Tellabs NEC, Turin, and other big names. Although they started off selling IP for both Altera and Xilinx, they have shifted almost exclusively to supporting Brand A of late.
Exact pricing for the TPWX3192 is hard to pin down since the size of the FPGA that holds it can vary significantly depending on the features you select. To give you some sense of what they cost, TPACK says that the volume price of the image and drivers for a fully-featured version of the mapper/switch, plus the FPGA is in the neighborhood of $1 k each. If you’re going to higher production volumes, moving your design to Altera’s hardcopy program could drop the cost into the $500 range.
Product Brief TPWX3192
Product Brief TPX3000
Product Brief TPW192
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