The Future of Electrical Signaling in a Post-10 Gbit/s World, Part V Signaling Standards Development for 25 Gbit/s Serial Links by David R Stauffer, IBM Microelectronics, ASIC Design Center
Editor’s Note: EN-Genius is proud to present this multi-part series on what lies beyond the 10 Gbit/s barrier for serial networking and interconnect technologies. Written by an eclectic group of leading technologists, this series will discuss the challenges they are facing as higher speeds push semiconductors to their limits and blur the once-tidy boundaries between the chips and the channels they drive.
In the previous installment, Eric Bogatin of Bogatin Enterprises and Mike Resso of Agilent Technologies presented a brief tutorial on what it will take to produce a model of a high-speed channel that’s accurate enough to perform useful simulation with, as well as the measurement techniques we’ll need to verify its actual characteristics. In this installment, David R Stauffer, a researcher at IBM Microelectronics, will look at the nature of the standards development process to identify some of the critical elements that will require special attention as well as potential pitfalls on the path to developing practical 25 Gbit/s serial links. We are grateful to Mr Stauffer for his insights on the subtle interactions between technology, politics and market forces that shape the standards we so often take for granted.
