The Future of Electrical Signaling in a Post-10 Gbit/s World, Part VI Getting to 25 Gbit/s With Existing Process Technologies by Brad Booth, Senior Principal Engineer, AMCC
Editor’s Note: EN-Genius is proud to present this multi-part series on what lies beyond the 10 Gbit/s barrier for serial networking and interconnect technologies. Written by an eclectic group of leading technologists, this series will discuss the challenges they are facing as higher speeds push semiconductors to their limits and blur the once-tidy boundaries between the chips and the channels they drive.
In the previous installment, David R Stauffer, a researcher at IBM Microelectronics, shared his insights on the nature of the standards development process. He also identified some of the potential pitfalls on the path to developing practical 25 Gbit/s serial links. In this installment Brad Booth, a Senior Principal Engineer at AMCC, uses Shannon's theorem to gain some insights about what it's going to take to push 25 Gbit/s worth of data across today's PCBs, backplanes, and cables.
