December 2008 - FPGAs under $5

When you factor in the breathtakingly-short development times and low tooling costs involved with putting your IP onto an FPGA, there are lots of applications which seem to beg for low-cost programmable silicon. Today’s tough economic conditions may also give FPGAs a boost over their non-programmable counterparts, according to Umar Mughal, Manager of Altera’s low-cost marketing group. Mughal points out that, in addition to saving the $1 - $2 million in photo mask charges, FPGA-based designs require far less engineering effort than hard silicon designs. And that’s not even counting FPGA 1 - 6 month design cycles that can help bring a product to market and have it producing revenue long before a conventional chip even reaches tape-out.

When they were introduced nearly a decade ago, Altera’s Cyclone I and Xilinx Spartan-1 series of value-priced FPGAs could compete directly with small ASICs in applications with production volumes as high as 100 k units. Altera and Xilinx report that the improvements in packaging and logic densities available in their second-generation series routinely enabled economical use of their FPGAs in products enjoying 250+ k unit sales, and even some applications with production runs in the millions. Altera’s Mughal reports that subsequent improvements in logic density and packaging in their Cyclone III series is making production runs of tens of millions practical.

These days, designers considering low-cost programmable solutions have a wide range of options to choose from, including devices capable of supporting complete embedded computing systems, powerful signal processing elements and devices priced at around $1 (and sometimes much less) that have enough gates to handle real-world interface and bridging functions. It’s also nice to know that using these low-cost chips does not mean you’re stuck with second-string design tools since most of these devices use the same powerful development suites and verification software packages that were created for their more expensive cousins.

In this report we cannot hope to cover all the options available to you in the rapidly-expanding universe of low-cost FPGAs, but you’ll definitely get a good sense of the exciting possibilities available to you.

Actel Corporation

Actel’s low-power, non-volatile Flash-based technology is the basis for their low-cost FPGAs which have instant-on capability and don’t require an external Flash chip to store their configuration code. Actel further reduces overall system cost by making a portion of their integrated Flash memory (typically 1024 bits) available to users for storing anything from unit serial numbers, configuration information, to calibration data. These rugged little devices are available in automotive (T-Grade) and military temperature grades and are naturally resistant to damage from high-energy neutrons, making them a good choice for many space applications.

Their ProASIC3 series supports the ARM Cortex-M1 and ARM7 soft processor IP cores, making them ideal for economical embedded solutions. It also supports a built-in AES decryption engine and a Flash-based AES-128 key for secure remote field updates over public networks with encrypted bit stream. The ProASIC3L branch of the ProASIC family includes a proprietary FlashFreeze mode that allows the devices to switch between active and static states within 1 μs while retaining register and SRAM content. This feature simplifies power management which eliminates the need to turn off power supplies or clocks. Most of the ProASIC3 family members have functional counterparts in Actel’s ultra-low-power IGLOO series which boasts even lower operating and static power and standby power as low as 2 µW.

Using economical FPGAs does not mean having to use low-end development tools. Actel’s Libero IDE handles all aspects of the design flow design from synthesis and simulation, through floor planning, place-and-route, timing constraints and analysis, power analysis, and program file generation. The latest version, Liberto 8.5, includes support for RTAX-DSP FPGAs enabling DSP development for the first time on the RTAX family with the implementation of an 18 bit x 18 bit math block that supports simple signed 18 x 18 multiply, dual signed 9 x 9 multiply, multiply plus accumulate and cascaded multiply applications.

Actel’s ProASIC3 family offers a wide choice of sub-$5 products, beginning with a 10 k gate device that costs $0.49 in 250 k piece lots. Other ProASIC3 devices are available with up to 3 M gates and 620 I/O lines. Their IGLOO series also offer several devices that cost under $0.99 in similar volumes. Further details on Actel FPGA products and development tools can be found via the links in the resource section at the end of this report.

Altera Corporation

Over the past few years, Altera has been as aggressive about adding performance and value to their budget-conscious Cyclone FPGAs and MAX PLDs as it has been with their ultra-premium Stratix devices. Because the Cyclone III series shares the same advanced sub-micron processes as its big-ticket brethren, even the smallest device packs 5 k LEs and enough hard logic DSP blocks and memory that they have become very popular for handling SD video processing tasks. Other family members offer LE counts of up to 120K k, along with hardwired embedded multipliers PLLs, and blocks of embedded RAM. It’s no wonder then that some of these larger members of the Cyclone 3 family are finding applications in HD video processing.

Cyclone’s high logic density also makes it possible to support soft processor cores – even on smaller, modestly-priced devices. Altera’s Nios II core was designed specifically to make efficient use of precious programmable gates and requires 500 - 2 k LEs (depending on peripherals and other features) so that it fits comfortably in even the smallest FPGA. Royalty-free and supported by a suite of free development tools, Nios has become so popular that Altera estimates around 50% of all recent Cyclone designs include at least one processor -- and the percentage is climbing.

If you prefer developing your software around a standard processor core, Altera has teamed with IP Extreme to offer a soft version of the popular Freescale ColdFire architecture free of charge. IP Extreme’s core fits the FPGA market very well because of its gate efficiency. The logic for the ASIC core was modified to work well in FPGAs and to be easily digested by Altera’s SOPC Builder and Quartus synthesis tool. When implemented on a Cyclone III FPGA, the basic ColdFire processor core uses around 6 k LEs and can support clock speeds of around 80 MHz. Developers will also appreciate the huge ecosystem of Freescale tools behind it, including their Code Warrior suite. Third-party operating systems are available from Green Hills, GNU, Wind River, and the Nucleus RTOS from ATI/Mentor.

Altera’s humble MAX CPLDs underwent a radical transformation with the introduction of the MAX II series that abandoned their traditional architecture and adopted standard SRAM-based FPGA technology that’s loaded at power-up using embedded Flash. Moving to an FPGA-based architecture reduced MAX II dynamic power by more than 90% over the MAX I series but it suffered from increased static power until the introduction of the MAX IIz series which boasts idle currents as low as 10 µA for the smallest device. Available in densities as high as 2200 LEs, its possible to implement a NIOS processor (or two) on some of the larger MAX II devices, but you will have to add your own external RAM.

So, what exactly can Altera give you for $5? As with any IC what you get is very dependent on how many you’re buying. Assuming your project will need a relatively modest 250 k units, a bit less than $4 will get you Altera’s Cyclone 3C5 which offers 5 k LEs, 400 kbit of on-chip RAM, 2 PLLs, and twenty-three 18 x 18 multipliers. It comes in an 8 mm2 package whose compact footprint is well-suited for volume-critical handheld consumer equipment where it is commonly used as an embedded controller, or as a display driver in cell phones and navigation systems. The 3C5 is also finding lots of work as a display controller for larger flat panel LCD displays as well as a per-pixel intensity compensation controller in plasma screens.

For around another dollar, you can bump up to the Cyclone 3C10 whose larger logic capacity and embedded DSP blocks are making it a popular choice for functions like image processing  (SD/HD conversion) and image enhancement. Designers find it’s especially useful in emerging applications where a simple firmware upgrade can allow a product to run the latest algorithms or track evolving standards.

Weighing in at $1.50 (and under $1 in higher volumes) is the MAX 240z, the smallest member of the MAX family. In addition to several hundred LEs worth of programmable logic, some of its more common uses are as a 4-channel SDIO mux, an audio buffer, or as a custom LVTTL/LVDS I/O expansion device. The MAX240z is also commonly used for power management functions in computers and networking equipment to handle power sequencing and fault monitoring tasks. Altera says that larger MAX devices are finding homes in handheld radios and games, wireline access equipment, femtocells, video conferencing equipment, and compact video cameras.

Like most other programmable logic companies, Altera’s learned that it takes more than making low-cost chips to gain the acceptance of engineers who are used to buying merchant silicon or rolling their own ASICs. Altera and most other vendors have invested heavily in design tools, development environments, IP libraries, and reference designs that help chip designers transfer their skills to FPGAs. For example, their DSP Builder tool allows designers to stitch together IP blocks without resorting to HDL/Verilog programming using a GUI design interface that works with Mathworks’ Simulink and Altera’s own SOPC Builder. To help build potential customer confidence and get designs off the ground quickly, Altera offers a wide selection of general-purpose and application-specific development kits, priced from $50 to $500).

See the resource section at the end of this report for links to product information.

Lattice Semiconductor

Much of Lattice’s ability to successfully compete with FPGA giants Altera and Xilinx has involved delivering more functionality and features per dollar, so it’s no surprise that their ECP2 line offers several innovations that Lattice feels give it more functionality and performance than comparably-priced Cyclone and Spartan devices. The ECP2 hardware DSP block has been crafted to deliver more performance and features than the simpler multipliers found in some other low-cost FPGAs. The block includes multiplier, adder, accumulator elements, and pipeline buffers to form a full MAC block instead of using precious programmable that might not run as quickly as a hardware core.

The ECP2 family also offers higher-speed I/O than commonly-found on low-cost products. Its memory controllers can run at up to 533 Mbit/s, and its LVDS-based I/O can run up to 1 GHz. The current version of ECP2 can only support static alignment (required for limited de-skewing) so its utility in connections like SPI 4.2 is limited to lower speeds (350 MHz or below). But that’s still fast enough to be extremely handy in lots of applications including custom I/O and connectivity as well as memory controllers. Its high-density LVDS I/O is a natural fit for the 7:1 multiplexed connections that are still popular for driving smaller LCD displays. These low-cost devices are also still enjoying the popularity they’ve traditionally enjoyed in networking/storage applications.

Lattice also produces the ispMACH 4000 series of PLDs which are ideal for low power, high volume portable applications. They offer typical standby current as low as 10 µA and operate from a nominal 1.8 V power supply with operation extended down to 1.6 V to accommodate extended end-of-battery-life voltages. The ISPMACH family also offers enhanced system features such as Power Guard dynamic power reduction lowering power consumption by selectively disabling unused input pins so their switching does not consume dynamic power needlessly. Other value-add features include a per pin pull-up, pull-down, or bus keeper control; an on-chip user oscillator and timer; and input hysteresis.

Just before this report went to press, Lattice announced two new members in its ispMACH 4000ZE series, the compact members of their ultra low power CPLD family. These devices are housed in space-saving UCBGA (ultra chip scale BGA) packaging that makes them an ideal choice for mobile phones and other handheld applications. The latest members, the ispMACH 4064ZE and the ispMACH 4128ZE device are now available in volume production as are the other devices in this product family. The ispMACH 4064ZE device is available in UCBGA-64 and the ispMACH 4128ZE device is housed in UCBGA-132, and have high-volume pricing as low as $0.85 and $1.60, respectively.

Lattice is also very enthusiastic about its so-called mid-range FPGAs, using low-cost products to do the work previously done only by high-end chips. While some of the ECP2 family members do run over $5, they still provide an extremely cost-effective alternative to the FPGAs and ASICs commonly used to do baseband & RF processing in both macro basestations and micro/femtocells. In smaller stations with lower channel densities, FPGAs can economically support some baseband and RF processing functions and help cut power requirements enough to enable solar operation. Many of these applications require support for standards-based high-speed SerDes-based interconnects like HDMI, DisplayPort, Ethernet, PCIe, SRIO, and CIPRI. These functions are available on their ECP2M family which includes integrated SerDes transceivers. Although there are presently no ECPM2 devices available for under $5 there are many devices priced under $10.

See the resource section at the end of this report for links to product information.

Xilinx Inc

There’s also been a revolution at the bottom taking place at Altera’s arch-rival, Xilinx, both in their CoolRunner CPLDs and their Spartan series of value-priced FPGAs. Instead of simply trying to cram as much functionality as possible onto an inexpensive chip Xilinx has carefully re-engineered their Spartan family to include innovative features that can reduce both development time and total system solution cost. Dave Myron, Xilinx Senior Marketing Manager for High Volume Products, says that their latest generation of Spartan FPGAs have been designed to absorb as many functions as possible (both logical and electrical) and include features that shorten and simplify their customers’ design cycles. Myron says that the third leg of their strategy is to make extensive use of commonly-used programming tools like Linux in their own development resources and reference designs.

Some of the least glamorous but most valuable improvements to Xilinx’ Spartan series are the silicon-level features that help minimize external component count and insulate the designer from most of the unique (and painful) power supply requirements that FPGA devices often have. Instead of the specialized power inputs that some devices need, Spartan power inputs include on-chip regulators and filters that allow it to use standard supply voltages and tolerate the 5% - 10% variations that are so common in many applications. Although it’s not obvious at first, these simplified power supply requirements can dramatically cut BOM costs by eliminating the external regulators and filters sometimes necessary with other chips.

Spartan devices also include robust true 3.3 V I/O logic outputs and differential I/O transceivers that include internal crossover termination resistors. Both I/O types are built with high drive output capability that eliminates the need for external buffers in most applications. The pennies that theses features can shave off a design’s BOM are multiplied by the reduced board space and assembly costs so that the savings can add up quickly. Xilinx also paid attention to supporting pinouts for their chips that enable simpler circuit board layouts and can minimize the number of layers required to implement a design.

Xilinx think-outside-the-chip approach also extends to minimizing system power consumption – a critical element of handheld/portable designs. The new Spartan devices include a suspended state mode that allows the device to hibernate without losing its programming or generating glitches on the outputs. In this standby mode members of the Spartan family can remain a clock cycle or two away from being ready to run while drawing as little as 11 mW. Xilinx has also included updates to Spartan architecture that allow parts of the chip that are not currently being used to have their clocks turned off for minimum dynamic power consumption. Xilinx’ compiler has also been enhanced to optimize power consumption while still allowing designers to make trade-offs between speed or gate utilization.

Xilinx has packed the low-cost Spartan series with high-value hardware logic cores for commonly-used functions such as clock management units (DLLs), BRAMs (for single/dual-port memories and FIFOs), and simple multipliers that can conserve programmable logic and operating power. One branch of the Spartan family features collections of dedicated multipliers and DSP blocks that support applications like video, medical imaging, surveillance cameras, and military radio systems. Spartan’s feature-rich DSP elements are much more than simple multipliers and can save from 50 - 1300 logic cells in a typical application. Besides the usual baseband and speech processing tasks, the cores have also proven very useful in display drivers where they handle functions like pixel interpolation – a very handy feature for HD video and medical imaging applications. Higher-end (more than $5) Spartan family members can support up to 30 GMACs for advanced medical, wireless and military applications.

The Spartan family does not offer the Power Architecture processor cores included in some of their high-end Virtex series but their royalty-free MicroBlaze soft core is well supported and can be built using as few as 4 k LUs. Even the most feature-laden MicroBlaze cores can be built using 6 - 7 k LUs, allowing you to have a Linux-capable processor that can easily fit on a $5 part.

Spartan has also been engineered to provide security for the IP that you’re entrusting to their chips. Many of the Xilinx sub-$5 parts include security features to discourage IP theft tactics like cloning or over-building, and to prevent reverse engineering or any other form of tampering with the code resident on the FPGAs. For applications requiring hardware-level security, Spartan offers a non-volatile embedded Flash option to keep all your code and data inside the package.

Like Altera, Xilinx understands that FPGAs are only one part of the design chain and have invested heavily in extensive tools, training, design support, as well as helping promote lots of OEM and third-party IP and software. Development kits featuring Spartan FPGAs start at $189 and a kit featuring a complete video signal processing lab is only $1500. If you want to get your feet wet at the lowest possible price Avnet offers a series of inexpensive third-party development boards that start at $39.

Xilinx claims to have the largest selection of IP and reference designs of any FPGA vendor. Their IP offerings range from small functions like multipliers to gamma table correction and Reed-Solomon decoders. These IP building blocks and a large library of reference designs for many common applications help accelerate design cycles and supplement the human resources of thinly-staffed engineering groups. For the parts of your design you need to develop yourself, you can use the Xilinx WebPack GUI-based design tool suite. The basic version is suitable for many simple designs and is available as a free, downloadable file. The premium WebPack suite includes an ISE design tool suite that includes advanced timing and power analysis tools, a ChipScope internal logic probe, and the Xilinx PlanAhead partitioning tool.

Spartan’s lowest-priced device is the 50A which has 1500 logic cells and costs under $1 (in 500 k-unit quantities). For simple applications which need basic low-speed logic (100 MHz and below), CoolRunner CPLDs offer lots of options in the sub-$1 region. They also boast lower static and dynamic power (µA range for static) – a feature that still makes them very popular as glue/gasket elements in cellular handsets and in peripheral connector/expander applications.

A full set of links to information on Xilinx products can be found in the resource section at the bottom of this report.

Low-Cost FPGA Resources: Handy Links to Vendor Product Information

Actel

• Actel ProASIC low-power FPGAs
• Actel IGLOO ultra-low-power FPGAs
• Actel Libero IDE and Design Software Suite
• Actel Starter Kits and Development Tools
  

Altera

• Altera Cyclone III FPGAs
• Cyclone III Starter Kit
• Altera MAX IIz PLDs
• Altera MAX II Development Kit
• Altera DSP Builder Tool
• Altera SOPC Builder Tool
• Altera Nios II Embedded Processor Evaluation Kit, Cyclone III Edition
• IP Extreme ColdFire Processor Core

Lattice Semiconductor

• Lattice ECP2 FPGAs
• Lattice ECP2/M SerDes-equipped FPGAs
• Lattice MACH 4000Z Low-Power PLDs
• Lattice MACH 4000ZE Ultra-Compact Low-Power PLDs
• Lattice ispLEVER Design Software Family
• Lattice Development Kits and Hardware
  

Xilinx

• Xilinx Spartan-3A FPGAs
• Xilinx Altera Spartan-3A Technical Overview
• Xilinx Spartan-3AN (Non-volatile) FPGAs
• Xilinx Spartan-3A (DSP-oriented) FPGAs
• Xilinx CoolRunner CPLDs
• Xilinx Development Tools
• Xilinx IP Library
• Xilinx Hardware Development/Evaluation Kits