|
 |
programmablelogicZONE Products for the week of February 2, 2009
Xilinx Says…
Two Next-Generation FPGA Families to Enable New Targeted Design Platforms
New Virtex-6 and Spartan-6 FPGA families lay foundation for new methodologies that bring ease-of-use and more productivity to applying programmable logic to system-level design.
Xilinx has introduced the next generation in the company’s flagship high-performance Virtex and low-cost Spartan field FPGAs, the foundation for a new generation of ‘targeted design platforms’ that will enable system designers to increase productivity and minimize development costs. With programmability increasingly becoming an imperative to electronic manufacturers’ ability to keep their innovative edge under challenging business and technological environments, these new targeted design platforms from Xilinx and its network of third parties will provide system designers with simpler, smarter and more strategically viable methodologies for creating FPGA-based system-on-chip solutions targeting a wide variety of markets and applications.
The Virtex-6 and Spartan-6 FPGA families build upon 25 years of Xilinx market and technology leadership with over 10 generations of FPGAs. These new families exploit the performance and cost benefits of proven advanced process technologies from UMC and new foundry partner Samsung to meet the insatiable global demand for higher bandwidth and greater performance at lower costs with less power for myriad end markets, ranging from automotive, consumer and wired/wireless communications to aerospace and defense.
“We are reaching the tipping point at which FPGAs become the prevailing silicon platform of choice for electronic manufacturers who need customization to differentiate their products, but are faced with incredibly unattractive ASIC development costs,” said Moshe Gavrielov, Xilinx president and CEO. “But in order for customers to increase their adoption of FPGAs, it’s essential that we provide a comprehensive design environment that enables global design teams to address the ‘programmable imperative’ and deliver products faster under these challenging economic and business conditions.”
The Programmable Imperative
As Moore’s law continues to deliver the benefits of higher chip density and performance along with the challenges of increased development and manufacturing complexity, the industry is seeing increasing adoption of FPGAs for next-generation system designs in lieu of traditional application-specific integrated circuits (ASICs) and application-specific standard parts (ASSPs). In fact, Gartner, Inc. predicts the ratio of FPGA designs to ASIC designs was about 25 to one in 2008 – highlighting a programmable imperative trend that the research firm expects to continue for the foreseeable future.
Addressing the programmable imperative requires a two-fold commitment. The first is delivering programmable silicon innovations that supply industry-leading value for every key figure of merit against which FPGAs are measured (price, power, performance, density, features, and programmability). The second is to provide the people who build electronic systems with tools, methodologies and IP for enabling FPGAs to deliver on their promise of fast-time-to-market and flexibility.
Targeted Design Platform
The Xilinx targeted design platform strategy encompasses the integration of five key elements:
- New Xilinx Virtex-6 and Spartan-6 FPGAs
- Design environments supporting and integrating industry-proven methodologies
- Scalable boards and kits adopting the industry standard FPGA Mezzanine Connector
- Socketable intellectual property (IP) cores
- Robust reference designs
Each of the elements, excluding the Xilinx FPGA device, is delivered by Xilinx or its third-party network and is supported by a robust ecosystem of design service expertise. Targeted design platforms enable software and hardware designers alike to leverage open standards, common design methodologies, development tools, and run-time platforms. This allows designers to spend less time developing the infrastructure of an application and more time building differentiating features into the end application.
Xilinx Virtex-6 and Spartan-6 FPGA Families
The mix of programmable logic and configurable hard IP built using the latest process technologies from UMC and Samsung enables Virtex-6 and Spartan-6 FPGAs to deliver twice the capacity at half the power consumption compared to previous families. Xilinx uses multiple foundries to provide the best technical solution for its customers. Both foundries are aligned with Xilinx’s strategy to optimize for power, performance, and cost and are recognized by the industry as proven manufacturers with well-established, low power, and advanced process technology.
With up to 760K logic density and more than 38Mbit of BlockRAM and 2,000 DSP slices, these new Xilinx devices set new benchmarks in on-chip performance. In addition, the new families offer up to 64 GTH transceivers that run up to 11.4 Gbits/s, enabling support for OTU (optical transport unit) specifications for the optical transport market, PCI Express-compliant hard blocks supporting root port functionality, and dedicated DDR3 memory controllers. These features help design teams keep up with the demands of bringing systems together, whether over a backplane, across fiber or copper, chip-to-chip, or connected to the latest high-speed memories available. With the new device families, system designers can also take advantage of more than 100 IP cores and reference designs across Xilinx FPGA families and development platforms.
For more information, go to http://www.xilinx.com/6 and reference separate press announcements, “New Xilinx Virtex-6 FPGA Family Designed for Satisfying the Insatiable Demand for More Bandwidth and Lower Power” and “New Xilinx Spartan-6 FPGA Family Brings Low-Power, Connectivity, and High-Performance to Cost-Sensitive Electronic Systems.”
EN-Genius Says…
Many of the improvements that Xilinx has conferred on its latest generation of FPGAs are the predictable, linear sort of bumps in performance, integration, and power you’d expect in a highly-competitive, rapidly-maturing market. The addition of SerDes capabilities to its value-priced Spartan line was almost as easy to anticipate, given arch-rival Altera’s introduction of its Arria series (reviewed here May 2007). What was less predictable is the massive structural alignment between the Virtex and Spartan platforms so that they now share a common design architecture, tool suite, and IP base, a move that will surely benefit both Xilinx and its customers. The other pleasant surprise in this announcement is the new way they’ve oriented both their products and support tools around specific application sectors. As we’ll discuss shortly, the dramatic upheavals in their tool chain and development platform ecosystem should help accelerate the design process for FPGA-based applications, an important piece of ammunition for Xilinx’ ongoing assault on the ASIC/ASSP market.
All members of Xilinx’ value-oriented Spartan-6 family now share a common internal logic structure with their premium-priced Virtex-6 cousins. It’s an enhanced version of the column-based architecture originally developed for the Virtex-5 series. The new 6-LUT configurable logic blocks have twice as many outputs from their internal logic than the previous generation. Improved routing between blocks has contributed to both series’ higher performance and lower dynamic power. The only places where the two families really differ architecturally are in some subtleties in their clocking/PLL schemes and where I/O is located on the chip. The Virtex line sticks to its original column-based scheme that puts I/O on two sides of the device while Spartan takes a ring-based approach which wraps I/O around all four sides of the chip.
Building their products from columns of LUTs, block memory/FIFOs, DSP and I/O, elements has allowed Xilinx to quickly produce variants of its existing product lines to address specific market segments. One example of this flexibility is the recently-introduced V5 TXT family which is specifically designed to address the need for protocol bridging, MAC functions, and other elements required to support 40 – 100 Gbit/s IP streams in next-gen telecoms equipment (see my September 2008 review for details).
All these under-the-hood improvements will eventually help Xilinx win new customers and open up new markets, but the biggest news for the average engineer is that the budget-priced Spartan-6 family is now available with high-speed serial I/O capability. Equipped with either two or four 3.125 Gbit/s SerDes transceivers, the Spartan-6 LXT series can be configured to support PCI Express (Gen 1), Serial RapidIO, SATA, and most other 2.5 Gbit/s serial protocols. With so many applications using PCIe as their interconnect of choice, Xilinx was smart to equip the LXT series with hard-coded logic cores that support MAC and transaction layer functions for PCIe Gen1 downstream (endpoint) nodes. The gate and power savings afforded by the hard PCIe MACs should help Spartan-6 LXT find its way into the growing number of high-volume applications that take advantage of the protocol’s high capacity and low cost of implementation. If you don’t need PCIe or other high-speed interfaces, the Spartan-6 LX series gives you all the features of its SerDes-equipped counterpart, except for the transceivers.
The other major enhancement to the Spartan-6 platform is a hardened memory controller core that gives you a simple interface to your choice of DDR1/2/3, or mobile DDR memory. Spartan’s lower speed range (250 - 300 MHz) is more than enough to deal with the speed range of the commercial memory it talks to. The controller supports transfer rates of up to 800 Mbit/s making it an ideal way to implement a low-cost buffer to supplement the FPGA’s on-chip memory.
Although Lattice’s low-cost SerDes-equipped LatticeECP2M devices (reviewed here October 2006) have more than a two year lead in this market, Xilinx’ solid performance and higher logic densities could threaten whatever sockets Lattice has managed to garner unless they can do something else to add value to their innovative products. But Xilinx won’t be able to rest on its laurels too long since its arch-nemesis Altera has just announced several updates to its product offerings (see their February 2 release), including improved versions of its mid-range Arria series that could closely match Spartan’s price/performance range.
There have also been big doings on the upper end of Xilinx product line with overall improvements to the platform and a re-segmentation of the product mix to align with their domain-oriented market focus. The Virtex- 6 FPGA family consists of three platforms built around different feature mixes to suit specific constellations of customer applications:
- The Virtex-6 LXT series’ mix of logic elements has been optimized for applications that require high-performance logic, DSP, and serial connectivity. It’s equipped with the same low-power GTX 6.5 Gbit/s serial transceivers derived directly from the Virtex-5 series.
- The Virtex-6 SXT series has a mix of features intended to support high-performance DSP applications. Like the LXT family, it offers high-speed serial connectivity with low-power GTX 6.5 Gbit/s serial transceivers.
- The Virtex-6 HXT series has been optimized for communications applications that require the highest-speed serial connectivity with up to 64 transceivers, including its new GTX serial transceivers capable of supporting data rates of up to 11.2 Gbit/s
In the move to the V6 platform, all Virtex family members got to enjoy a few basic improvements to the V5’s already-capable architecture. Its 25 x 18 DSP blocks now include a pre-adder that cuts the number of clock cycles required to perform symmetric filtering operations (add, multiply, add) that are essential in video processing and wireless applications. In some applications, the pre-adder allows a single V6 DSP slice to do the work of two V5 slices.
The Virtex-6 now offers three speed grades of SerDes I/O, each of which has been tweaked to serve a particular set of applications. The first member of the family is a mildly-upgraded version of the GTX transceiver originally developed for the V5 platform with a slightly-broadened speed range of 150 Mbit/s to 6.5 Gbit/s. In most respects, it is functionally identical to the Virtex-5 transceiver, including a sophisticated receive equalizer which employs a combination of digital-decision feedback and linear elements. Power consumption has improved slightly, with a maximum draw of under 150 mW when running at full speed.
In a move that echoes Altera’s strategy for its Arria series, the 3.2 Gbit/s GTP transceiver available in the Sparten-6 LXT family has been tuned for low power consumption (100 mW/channel) but is still fast enough to support first-generation SerDes-based interfaces running at 2.5 Gbit/s, including PCIe (Gen1), SRIO, XAUI, SATA and low-end CPRI.
For those living on the bleeding edge, the 11.2 Gbit/s speeds offered by Xilinx’ new GTH transceiver will allow you to support 10G SONET and Ethernet applications without a fuss. It’s also been designed to interface directly to 10G optical modules: a handy feature that eliminates the need for external logic shims or buffers. The GTH receiver is very similar to the GTX but its equalizer has been enhanced with several extra stages of DFE and its PLLs have been precision-tuned for low jitter. As one would expect, this extra performance requires extra power so these bad boys draw a bit under 250 mW when running at 11.2 Gbit/s.
As part of the overall upgrade, the all Virtex-6 transceivers now have enhanced PCIe MAC logic that supports both end point and root node capability. The other new feature of note is that each transceiver has its own PLL (V5-shared PLLs among two or more transceivers), enabling channels to be used in bundles or singly as needed.
Xilinx has applied similar efforts to improving its development environment, making it easier to use by people just getting their first taste of FPGA-based designs and simplifying the lives of those having to crank out ever-larger designs. Part of the strategy is to wrap their tools within so-called personae that allow a developer to program from their existing expertise. In other words, traditional chip designers will be able to use VHDL or Verilog, but people more accustomed to DSP design will be able to use algorithmic design entry tools like Matlab/Simulink. The current system still requires some fiddling before the final programming code can be generated for your target chip, but it seems much easier to use than what’s currently available.
Similar efforts have been made to produce a tool chain that works across both product lines. Since Spartan and Virtex now share a common set of core logic elements, you can use the same IP, design tool chain and methodology for both families. About the only inconvenience is that whatever IP you use still needs to be qualified and verified separately for each platform.
There has also been lots of work on the evaluation and analysis tools. Eventually, connectivity-oriented designers will be able to seamlessly access signal integrity analysis tools and simulators from within Xilinx’ IDE suite and embedded designers will be able use the same interface to evaluate trade-offs between soft logic and software implementation of functions. Xilinx is in the process of making sure that outputs of different elements work together with common shared data formats and that their elementary IDE provides a common interface to all tools. The present setup still requires judgment calls about which tools to use and how to use them but I’d expect that future releases will fix this.
It’s a bit more difficult to say whether Xilinx’ aggressive restructuring of their development kits, higher-level IP, and reference designs into so-called domain-specific and market-specific constellations will help rationalize their marketing and design support efforts. At first glance, slicing up their wide universe of applications into three domains (embedded systems, DSP, and connectivity), each with their own dedicated development platforms looks like a great way to help FPGA novices get their feet wet, and help those with FPGA experience reduce their development times dramatically. Likewise, their growing collection of near-turnkey application-specific reference designs should help shorten the concept-to-product cycle, even if I worry a little about whether some emerging applications will be under-served.
Regardless of whether or not this new scheme is the perfect way to segment their tools and products, it’s probably a significant improvement over their existing piecemeal infrastructure that grew in response to the new markets for FPGAs that have emerged over the last few years.
Spartan-6 devices are sampling to customers now. Initial Virtex-6 device samples will be available in the second quarter of 2009. Pricing in high volume production timeframe will range from $3 – $54 for Spartan-6 and from $57 – $2100 for the Virtex-6 family. Device details and software support are available now through the Virtex-6 and Spartan-6 early access programs.
Xilinx targeted design platforms providing fully integrated software support, tested IP, and reference designs with boards and kits will be available in the second half 2009.
Product Page
|
|
|
|
|
