programmablelogicZONE Products for the week of February 16, 2009
Altera Corporation Says…
Stratix IV GT and Arria II GX FPGAs Expand Industry’s Broadest Integrated Transceiver Portfolio
Stratix IV GT FPGAs: only FPGAs with Integrated 11.3-Gbit/s transceivers Arria II GX FPGAs: optimized for applications requiring up to 3.75 Gbit/s
Altera Corporation has announced two new FPGA families with integrated transceivers. The new Stratix IV GT and Arria II GX 40-nm FPGA families join Stratix IV GX FPGAs and HardCopy IV GX ASICs to expand the industry’s broadest portfolio of transceiver FPGA and ASIC solutions. Altera’s portfolio offers transceiver speeds from 155 Mbits/s to 11.3 Gbits/s that address a wide range of applications, from cost sensitive video cameras to ultra-high-performance backhaul systems.
The Arria II GX, Stratix IV GT, and Stratix IV GX FPGAs and HardCopy IV GX ASICs utilize common transceiver technology and are supported by a common set of development tools that enable system designers to develop full system-on-chip (SoC) solutions. This portfolio delivers both FPGA solutions from 16K logic elements (LEs) to 530K LEs, and HardCopy ASIC solutions of up to 11.5 million ASIC gates.
The programmable fabric and integrated programmable transceivers provide designers with the flexibility needed to overcome unpredictable design requirements. Altera’s transceiver technology provides easy-to-use signal integrity features that accelerate product development, while consuming less power than competing solutions.
"Altera's expanded portfolio of transceiver FPGAs and HardCopy ASICs address the increasing market demand for a range of transceiver solutions. Since each application requires a unique set of features at specific performance, power, and price points, Altera developed this portfolio to provide optimal solutions to address a broad range of applications," said Danny Biran, senior vice president of product and corporate marketing at Altera Corporation. "These products offer superior signal integrity, the lowest jitter specifications, and broad high-speed I/O protocol compliance, alleviating the challenges facing designers of systems requiring transceivers."
The highest performing FPGAs available, Stratix IV GT devices are also the industry’s first FPGAs to include integrated transceivers operating at 11.3 Gbits/s. The architecture is optimized specifically for 40G and 100G applications such as communications systems, high-end test equipment, and military communications systems. Stratix IV GT FPGAs have 24 transceivers operating at 11.3 Gbits/s, and an additional 24 transceivers operating at 6.5 Gbits/s, to deliver the industry's highest bandwidth available. The Stratix IV GT devices also offer up to 530K LEs, 20.3-Mbits internal RAM and 1,288 18 x 18 multipliers.
Arria II GX devices are the lowest power 3.75 Gbits/s transceiver FPGAs and are cost optimized for applications using mainstream protocols such as PCI Express (PCIe) and Gigabit Ethernet (GbE). They feature up to 16 3.75- Gbits/s transceivers, 256K LEs, and 8.5 Mbits of internal RAM. In addition, the Arria II GX FPGAs also support targeted protocols such as CPRI for LTE and WiMAX wireless infrastructure access equipment, GPON and XAUI for wireline infrastructure access and networking equipment, and triple-speed SDI for broadcast and other video processing equipment. A collection of reference designs and design examples accelerates the development of solutions using Arria II GX FPGAs.
The FPGAs and HardCopy ASICs in Altera’s transceiver portfolio are supported by Altera’s new Quartus II design software version 9.0. The design software provides a single tool suite for all FPGA and ASIC products, complemented by one IP set and a common transceiver technology. Together, this delivers the "learn it once, use it everywhere" experience that increases system designer productivity while reducing time to market and engineering expenses. Altera also provides a suite of tools to ease transceiver integration and board design, including the Pre-Emphasis and Link Estimation (PELE) tool, the power distribution network (PDN) tool, and the Early Simultaneous Switching Noise (SSN) Estimator, as well as SPICE and IBIS simulation models and a board-design guidelines document.
With the introduction of these two new FPGA families, Altera builds on the existing Stratix IV GX FPGAs and HardCopy IV GX ASICs. Stratix IV GX FPGAs are the industry’s first and only available 40-nm FPGAs. HardCopy IV GX ASICs are the lowest risk ASICs with transceivers. Designers can prototype with the Stratix IV GX FPGA series and seamlessly migrate to HardCopy IV GX ASICs to achieve the lowest total cost, lowest risk and fastest time-to-market solution for their custom logic needs.
EN-Genius Says…
The simultaneous roll-outs of Altera’s Stratix IV/Arria II and Xilinx’s Virtex-5/Spartan5 (reviewed here February 2, 2009 platforms move the FPGA industry to a level of maturity where it is now a credible alternative to ASICs for a surprisingly-large number of applications. Although there are many obvious similarities in the way each company has positioned their next-generation products, Altera has done several important things to differentiate itself from its worthy competition and gain a dominant position in the struggle for this expanded market.
Although Altera does not have the application-specific internal architectures that its competitor offers, they’ve expanded the Stratix and Arria product lines with devices that have specific mixes of logic densities and I/O that create a wide portfolio of products that are fine-tuned to address a well-defined set of target markets in networking, communications, and signal processing. They’ve also added several important improvements to their I/O technology, the most significant of which is the 11.3 Gbit/s SerDes transceiver available in the GT family. Its speed and drive characteristics allow it to directly connect to QSFP and other 10G optical modules without external transceiver chips. The GT transceivers’ low jitter characteristics (sub-1 ps) allow multiple lanes to be ganged together to drive Interlaken or SPAUI interfaces at 40 & 100 Gbit/s, as well as 100G CFP modules.
Altera has been equally innovative with its mid-range GX transceivers which are now available on both the Stratix and Arria platforms. The GX’s maximum speed has been boosted from 3.2 Gbit/s to 3.75 Gbit/s and power consumption has been trimmed a bit. While they are pretty much identical on the outside, there are some important internal differences between the GX transceivers used in the Arria and the Stratix platforms. Most of these differences are because the Arria is designed to support a handful of mainstream protocols like PCI Express GbE, and XAUI while the Stratix parts are expected to handle a wider range of speeds and protocols in the more sophisticated applications they target.
Budget-conscious designers will appreciate that Arria II devices now include a hard logic core that implements the MAC function for PCIe Gen1, the protocol that Altera expects the chips will be most commonly asked to support. Like its more general-purpose Stratix counterparts, Arria can also implement MACs for most other common 2.5 Gbit/s serial protocols using soft IP. At the deep circuit level, the Arria devices use a PLL based on a ring oscillator while the Stratix GX’s PLL achieves a wider operating range by switching between a tunable ring oscillator and a varactor-tuned LC tank. The other significant difference is that Stratix receivers use a mix of adaptive and programmable equalization while Arria’s don’t have the adaptive elements.
By trading off a little flexibility Altera has been able to make Arria a bit more cost-effective to use in the mid-range applications which are dominated by moderate logic speeds (around 250 MHz) and PCI-Express I/O. This makes it a great fit for remote radio heads, DSLAMs, MSAN boxes and other access applications where cost, power and space are limited. Altera says that it is also well-suited for slower, simpler signal and image-processing applications that are not practical for the Stratix family to address.
Altera has done a great job of harmonizing its Stratix, Arria and HardCopy families, including the development tools. The release above gives you a blow-by-blow account of all the improvements that have been added to the Quartus design software but it’s worth noting the big strides they’ve made in signal integrity analysis. The Quartus 9.0 software allows evaluation of simultaneous switching noise, jitter, crosstalk, and other channel impairments. Quartus’s outputs can be used to feed the Pele link estimator tool to generate initial transceiver equalization and pre-emphasis settings that will allow you to get your backplane-based designs operational enough to begin whatever additional tuning they will require. To make your life even simpler, Altera is in the process of developing a set of board and high-speed channel design guidelines that will help take even more of the guesswork out of SerDes-based designs.
The significant expansion of their second-generation Arria product line and the addition of 11.3 Gbit/s SerDes capability to their Stratix series greatly widens their offerings at the top and bottom of the market – both in terms of speed and price. This, and improvements in the migration path to their HardCopy metal-programmable ASIC process, may be the elements that Altera has been looking for to change the role that FPGAs play in the mainstream electronics market. Despite their ambitious goals, Altera’s strong track record and conservative approach (if anything in 40 nm can be considered conservative) earn them a remarkably-low Saltshaker Rating.
The first Arria II GX device, the EP2AGX125, will ship in May 2009 with production devices scheduled for the fourth quarter of 2009. Budgetary pricing for the smallest device, the EP2AGX20, will start as low as $15 for 100-k unit quantities in 2010. All of the Arria II GX devices will be supported in the Quartus II design software version 9.0 in March 2009.
Product Page Stratix IV Series
Product Page Arria II Series
|
|
