programmablelogicZONE Products for the week of March 2, 2009
Lattice Semiconductor Says…
Industry’s Lowest Power, Highest Value FPGA Devices
SERDES-capable LatticeECP3 family consumes half the power and is half the price of competitive devices
Lattice Semiconductor Corporation has announced its third generation high value FPGAs, the mid-range 65nm LatticeECP3 family, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu’s advanced low power process technology, and is the only 65nm mid-range, high value FPGA family in the industry.
“Like our award winning LatticeECP2M devices before it, our LatticeECP3 family once again redefines mid-range, value-based FPGAs, not only by further reducing costs, but also by reducing static power consumption by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs. By making careful design choices and minimizing die size, we are able to offer designers the benefits of high speed serial I/O and processing capabilities, without the power and cost premiums typically associated with these types of devices,” said Sean Riley, Corporate Vice President and General Manager of High Density Solutions.
“Early Access” LatticeECP3 Customers React Enthusiastically
“…unprecedented power and performance results.”
“...the only FPGA that was able to meet our technical requirements….”
While the LatticeECP3 family is being formally announced today, for several months many Early Access Lattice customers have been experiencing first hand the low power and high value benefits that are the hallmarks of these new FPGA devices.
Shane Flint, Managing Director of Affarii, a provider of wireless transmitter and linearization solutions, said, “Implementation of our 4G transceiver design with Crest Factor Reduction and Predistortion functions in the LatticeECP3 FPGA has yielded unprecedented power and performance results. With sample rates up to 180Msps, LatticeECP3 performance exceeds that of commercially available ASSP offerings, and power consumption is 50% lower than previous Remote Radio Head designs using high-end FPGAs. Add to this the integrated SERDES supporting CPRI, OBSAI and Gigabit Ethernet, and we can offer a single chip processing solution that greatly reduces real estate, power consumption and implementation cost for wireless basestation vendors.”
Philippe Wetzel, CEO of Vitec Multimedia, a pioneer and worldwide leader in the digital video domain, said, “Vitec selected the LatticeECP3 in the summer of 2008 to support a technically demanding new product design. It was the only FPGA that was able to meet our technical requirements for 3G HDSI video, PCIe x4 and DDR3 at 800MHz, all on a low cost FPGA platform.”
Five LatticeECP3 Family Members
The five devices that comprise the low power LatticeECP3 FPGA family all offer standards-compliant multi-protocol 3G SERDES, the industry’s only DDR3 memory interface for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family’s high performance features include:
- 3.2G Gbps SERDES with 10GbE XAUI jitter compliance and the ability to mix and match multiple protocols on each SERDES quad. This includes PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO and Gigabit Ethernet.
- The SERDES/PCS blocks have been designed specifically to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.
- Compliance to the SMPTE Serial Digital Interface standard, with the unprecedented ability to support 3G, HD and SD/DVB-ASI video broadcast signals independently on each SERDES channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power.
- DSP slices allowing up to 36x36 Multiply and Accumulate blocks in each slice running at 500MHz. The DSP slices also feature innovative cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic.
- 800Mbps DDR3 memory interfaces, with built-in read and write leveling.
- 1Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high performance ADC and DACs.
With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging, applications.
Design Tool Support
The LatticeECP3 FPGA family is supported by the ispLEVER design tool suite, version 7.2 Service Pack 1, which also has been announced today. The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER software is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. The ispLEVER design tool suite includes Synopsys’ Synplify Pro synthesis for all operating systems supported and Aldec’s Active-HDL Lattice Edition simulator for Windows.
EN-Genius Says…
Just as Brand A and Brand X a have finally caught up to Lattice’s low-cost SerDes-equipped ECPM2 devices (first reviewed here October 2006) with their own value-priced Spartan and Arria series (chronicled in last month’s editorial) the insurgents from Hillsboro are back nipping at the Big Dogs’ rump from another weakly-guarded front. According to Lattice, their new ECP3 line of mid-range FPGAs targets moderate-to-high density applications with enough speed and overall performance to serve most mainstream designs at a much better cost than an Arria II/Spartan-6 solution. Lattice has tailored its offerings to be especially attractive to wireless infrastructure applications but by delivering LUTs and DSP elements for the buck, low power consumption, and significant improvements in their tool chain, they offer a compelling value for many other cost-conscious applications where SerDes is the interconnect of choice.
The LatticeECP3 FPGA family represents a carefully-struck balance between cost, performance and power. For example, the low-cost wire bond packaging they use keeps their SerDes transceivers’ maximum speeds much lower than their bigger competitors’ devices that are packaged using direct-attach techniques. Nevertheless, Lattice has made some incremental advances in signal integrity and their overall transceiver design that they can now comfortably support the 2.5 Gbit/s rates required for commonly-used GbE, PCIe, SRIO and CPRI connections – and at a much lower cost.
At the same time, ECP3’s power consumption has been reduced to 90 mW and they now feature a clever word-aligner circuit that is expected to be very popular in cellular basestations which use multi-lane SerDes for most links between system elements. This small chunk of hard logic that works cooperatively with each lane to adjust offset to match help keep multi-lane links aligned - even if there is up to 10 bits worth of latency variation between links. This is somewhat similar to the lane alignment scheme featured in Xilinx’ new products but goes one step further by passing the latency information back to the transmit system so that it can adjust timing variations at the system level. Latency variation is also addressed at the bridge FIFO logic, commonly used as a buffer between system elements. If the FPGA/DSP fabric can support it, the bridge FIFO can be bypassed to remove a potential source of latency variation and allow both SerDes and DSP to use same clock domain.
Similar trade-offs are evident in the power/performance equation Lattice used to define the ECP3 series. The new family uses the same two-tiered architecture as the ECP2 series which limits the use of faster, higher-leakage transistors to critical areas of the SerDes, I/O and DSP blocks and lets slower, lower-leakage devices do the majority of the work. Nevertheless, Lattice says that ECP3’s programmable logic can be clocked at 200 - 250 MHz in typical designs and up to 350 MHz in small, closely-coupled blocks such as simple counters.
Now that all three companies offer SerDes capabilities in their mid-range FPGAs, you’d think it would be relatively easy to come up with an apples-to-apples comparison between them. Since Xilinx and Altera took rather different approaches to delivering a mid-range SerDes family it’s a bit more complicated.
ECP3 vs. Arria 2
Much of the genetic material that went into Altera’s Arria II GX family appears to be derived from their high-end Stratix line, so it’s no wonder why its logic and SerDes elements offer faster logic elements and better-performing SerDes transceivers than ECP3. Of course Arria’s performance-oriented guts are probably also why it consumes 20% - 100% more static power (the difference increases as logic and I/O counts grow) than an equivalent-sized Lattice part. ECP3’s publicly-announced pricing (in terms of equivalent LUTs/$) beats Arria’s public prices by 35%. It’s tough to say whether this price differential is simply because Altera rightly feels customers who need Arria’s extra performance are willing to pay for it or whether there are some underlying economics (such as larger die size or higher processing costs) driving the price differential. With no new devices to sample yet, Altera has not released any power consumption information but its estimated die size and advertised performance would lead one to guess that ECP3 probably uses 25% - 35% less power for an equivalent-sized device.
On the other hand, Lattice’s ECP3 series does not have the hard logic PCI Express MACs that Arria and Spartan-6 pack next to their transceivers. This means you’ll have to use some of your precious LUTs to implement the MACs you need, something that might narrow down Lattice’s logic density advantage in many real-world applications that involve PCIe. In its defense, Lattice says that they did include some hardened functionality for the DDR3 I/O to eliminate timing/skew problems at these speedy interfaces, leaving only the memory controller to be implemented in soft gates.
ECP3 vs. Spartan-6 LXT
Because Xilinx’ Spartan-6 devices were engineered from the ground-up as a cost-conscious solution, it’s easier to make a direct and dramatic comparison with ECP3. The most obvious difference is that Lattice offers more DSP elements (and memory) on an equivalent-sized chip – up to 80% more in the case of their 150 kLUT (logic cell) ECP3-150 and Xilinx’ XC6SLX150T. The DSP-rich logic mix seems to be a key factor in Lattice’s strategy to capture a large chunk of the 3G/4G wireless base station market which is one of the few bright spots in the troubled global economy. According to Lattice, equipment makers are finding that FPGAs are more cost- and power-efficient ways to implement many of the key baseband and RF functions that have been traditionally performed by DSPs.
Given Lattice’s focus on wireless basestations, it’s no wonder then that Lattice also tends to offer more memory and SerDes interfaces on equivalent-sized devices. Their smaller products have roughly the same number of transceivers but this changes as LUT count grows, with larger devices enjoying up to 40% more on-chip RAM and twice as many high-speed serial connections as their Spartan counterparts. Many members of the ECP3 family also offer more parallel LVDs and memory interfaces.
If nothing else, the extra memory comes in handy as buffer area or for storing intermediate results and other operators in DSP operations. The extra serial interfaces will be equally appreciated since modern basestations use SerDes-based standards (SRIO, PCIe, CPRI, OBSAI, and JESD204 to name a few) for nearly every intra-system interconnect.
I’m still awaiting detailed price and power information from Xilinx so an accurate comparison in these areas is not possible at this time.
Once again, I have to point out that this is not a one-sided contest and that the Xilinx devices enjoy several advantages. Even though I don’t have precise power dynamic numbers form Xilinx, I suspect that they will be pretty competitive with Lattice in terms of operating power. And much like Altera’s Arria devices, Xilinx’ Spartan-6 LXT series come with hard-coded logic cores that support MAC and transaction layer functions for PCIe Gen1 downstream (endpoint) nodes that save your programmable logic for more important purposes. When I asked Lattice about why they did not include MAC logic and if there were any plans to do so in the future they explained:
“We pioneered the hard logic concept with the FPSC family and then subsequently with the SC/M family. However, as with the ECP2M, the focus for the ECP3 is to provide the smallest, most effective die that will result in the industry's cheapest LUTs, and not to burden the die with additional ASIC gates.
“Here’s the question we had to ask ourselves: is the function that you are trying to build more economical to deploy on cheap LUTs, or do we put it on an ASIC block that will ultimately increase the die size? At least for this generation, we believe that it is the former.”
I also asked Lattice whether they had any plans to provide a clean migration path for ECP3 to be implemented in their metal-programmable MACO hybrid ASIC family. To my mind, it could help them compete with Altera’s HardCopy ASIC program that allows customers to cut the cost of their designs when production volumes are high enough to justify it. Lattice did not share my sentiments and replied: “We do not anticipate hardening anything for now (never say never, of course), and we do not offer a migration path to structured ASIC technology – it would not make sense; the ECP3 is already low cost and meets some of the lowest price points in the industry.”
Given the stiff competition it faces from the two industry leaders, Lattice has done a great job in identifying important market opportunities and exploiting them to the maximum before the industry juggernauts can. Much like when they introduced their first low-cost SerDes products, Lattice is gambling that they will be able to lure both FPGA newbies and seasoned pros with a price/performance ratio that will be hard for their competitors to match. They are also smart for biasing their architecture towards wireless applications while still keeping them an excellent value in for general-purpose use.
The questions still remains however, whether Lattice will be able to pry enough existing Altera and Xilinx customers away from their familiar tool chains, design rules, and libraries of existing IP they’ve accumulated. For the short term, however, Lattice will enjoy the advantage of immediate availability because they’ve already had samples in the hands of select customers since September of 2008. As of this writing, production volumes of 70kLUT and 90 kLUT ECP3 products will be in manufacturer’s hands and being used in production designs. The remainder of the family is scheduled for sampling or production by mid-2009.
Production devices are available now. In 25-k piece lots and in the FN484 wirebond package, the LatticeECP3-70 is priced as low as $35 and the LatticeECP3-95 as low as $50.
Product Page
|
|
