programmablelogicZONE Products for the week of March 19, 2007
Altera Corporation Says…
Industry’s First 65-nm Low-Cost FPGA
Cyclone III FPGAs deliver an unprecedented combination of power, functionality and cost for wireless, video, display and other cost-sensitive applications
Altera Corporation announced the immediate availability of the Cyclone III family, the industry’s first 65-nm low-cost FPGAs. Cyclone III FPGAs consume 75 percent less power than competing FPGAs and deliver 5K to 120K logic elements (LEs), up to 4 Mbits of memory and up to 288 digital signal processing (DSP) multipliers. At 20 percent lower cost per logic element than the previous generation, the Cyclone III family enables designers to use FPGAs in more cost sensitive applications than previously possible.
“We have received our first Cyclone III devices and are adopting them for our high-performance embedded motor control programs,” said Eric Wildi, chief electronics officer at Emerson Climate Technologies. “The compelling architecture innovations in Cyclone III FPGAs, such as performance and abundant memory, enable us to cost effectively deliver greater functionality compared to conventional microcontroller and DSP solutions.”
Leveraging TSMC’s 65nm low-power (LP) process, Cyclone III FPGAs offer low power, a rich supply of logic, memory and DSP capabilities. Cyclone III FPGAs enable more applications than any other low-cost FPGA family in the history of programmable logic.
“The Cyclone III family can handle more applications than any other competing solution because of its unprecedented combination of low power, high functionality and low cost,” said Jordan Plofsky, senior vice president of marketing at Altera. “More than 200 customers who participated in the Altera early access program are already designing Cyclone II FPGAs into a wide range of applications that target consumer, automotive, military, industrial and wireless communications markets.”
More Resources for More Applications
Here are just a few examples of what engineers can achieve exclusively with Cyclone III devices:
Software Defined Radio (SDR)
Cyclone III devices enable the integration of SDR waveforms in a single device for less than 0.5 W of static power. The Cyclone III family’s ability to deliver the necessary logic, memory, DSP multipliers and cost are unmatched in integrating these waveforms in a single device.
A prime example is Rockwell Collins’ secure mobile military communication programs, where size, weight, power and cost are the factors that matter. The Cyclone III family enables the company to design systems with best-in-class specifications in each of these areas, and ultimately enables new applications that were not possible before.
Deployment risk is another key factor, which Altera has reduced by delivering first Cyclone III devices to Rockwell Collins ahead of schedule.
Wireless:
Compared to the previous generation and competing products, the low power, high density and ample DSP capabilities of Cyclone III FPGAs allow designers to use the low-cost family in a broad range of new wireless applications, such as digital IF and baseband functions in wireless pico base stations.
Video and Image Processing:
Only Cyclone III FPGAs offer the right combination of DSP multipliers, memory and logic for video system I/O, video compression encoding, and video and image processing applications. In fact, customers can implement a full H.264 encoder for under $20 or implement high-definition (HD) scaling for under $5. “With the Cyclone III family, Altera has provided the first memory- and DSP-rich FPGAs that are ideal for cost-sensitive applications,” said Professor Stéphane Mallat, CEO of Let It Wave. “Using Cyclone III FPGAs enables Let It Wave to deliver our advanced video processing at price points that are attractive to the consumer market.”
Displays:
Cyclone III devices are optimized for display applications and are the first low-cost FPGAs to meet all 1080p HDTV performance requirements. Altera built the Cyclone III family with display-specific I/O interface support (mini-LVDS, Reduced Swing Differential Signaling and Point-to-Point Differential Signaling), more outputs per phase-locked loop (PLL) compared to the previous generation and dynamically reconfigurable PLLs to support changing refresh rates. As a result, customers can design a single platform for a wide range of display sizes and resolutions for as little as $4.
Customers can also use Cyclone III devices alongside existing ASIC/ASSP devices to improve picture quality and features. “The low power consumption and low cost of Cyclone III FPGAs make them attractive for many of our products. We have received our first devices and will be using them for video processing and driving the displays in our next-generation marine navigation products,” said Fabio Galli, hardware development manager for the Marine Electronics Division at global positioning system (GPS) technology manufacture Navman. “Also, the abundant memory and multiplier resources in Cyclone III devices enable us to use FPGAs in applications that would have previously required DSP processors or ASSPs.”
Customers can start designing for the Cyclone III family today in version 7.0 of the Quartus II design software (see related release) with support for all family members in the subscription and free web editions of the software. The Cyclone III family support in Quartus II Web Edition marks the highest device density available within any FPGA vendor’s free software package, enabling the largest number of designers around the world to access the entire range of Altera’s advanced 65-nm low- cost FPGAs. For a limited time, Altera is also making available to customers free ModelSim - Altera Web Edition software. In addition to the Quartus II software, Altera’s complete design environment includes access to a library of proven intellectual property, application-specific reference designs, low-cost development kits starting at just $199, and Nios II processors, the world's most versatile embedded processors.
EN-Genius Says…
Altera’s decision to move its commodity-grade Cyclone series to a 65-nm process is well-timed because it has avoided some of the early growing pains while keeping the products on an aggressive path to deliver more bang for the buck. The lower power consumption afforded by the smaller process geometry is probably just as important as price in the many applications that these devices are well-suited for.
The appearance of display-specific hardware features (tuned to support full 1080P HD displays) in some members of the Cyclone III family is one of several signs that it’s been heavily tooled-up to provide commodity-level replacements for custom ASICs and ASSPs. You get a wide range of capacities from 5 k to over 120 k LEs and up to 4 Mbits worth of embedded RAM. And if your application involves DSP functions, you’ll appreciate the 18 x 18 bit hardware multipliers (up to 288 on the largest chips) they’ve sprinkled into the mix. The result is a mix of higher functionality, lower cost and lower power that should help Cyclone find its way into applications where FPGAs were not previously practical.
As the release above indicates, Altera has gone out of its way to get software and hardware tools into the hands of designers that will make it easy to evaluate and use their products. They’re to be congratulated on giving away so much software that previously commanded premium prices as it will most certainly help jump-start lots of design projects. I also think that the low-cost development kits they’re offering will make lots of designers happy and help them win lots of slots. If the new kits are anything like the really nifty DE-2 development board (list price $269) I got to play with a while back, you’re in for a real treat.
Cyclone III significant power savings were accomplished by a combination of TSMC’s low-power process, and the optimization capabilities afforded by Altera’s Quartus II place and route software to deliver efficient solutions. But just to offer a reality check, the power savings are not uniformly dramatic across the entire product line. According to what I learned in my briefing, the power saving is mostly in the core logic so the new series begins to enjoy a significant advantage on chips with 25 k - 30 k logic elements (LEs), and improves as the logic density grows.
Using smaller geometries also gives the devices improved performance, with typical system speeds of 166 MHz and I/Os capable of running at up to 875 Mbit/s using a 200 MHz DDRII interface. Of course, the new Cyclone chips are still not as quick as their brethren in the premium-priced Stratix III series which offer 550 MHz DSP capabilities and advanced power management features. Cyclone devices also still lack on-chip GbE 2.5 Gbit/s SerDes capabilities that would make it a shoe-in for many applications involving PCI Express and Serial RapidIO. Altera says that they feel the speed range of their devices and package technology does not justify adding this capability but if a customer felt the need they could add it using external PHYs from TI Genesys. That being said, my handlers at Altera advised me to keep in close touch for some interesting news soon.
The Cyclone III EP3C25 is sampling with production scheduled for August 2007. The remainder will be in production by the end of 2007. Pricing will be $4.00 for the EP3C5E144C8 for 500-k piece lots.
Data Sheet
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