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programmablelogicZONE Products for the week of March 31, 2008
Xilinx Says…
Integrated Design Tools Suite Provides Breakthrough Improvements in Productivity, Performance & Power
Single unified delivery of total customer solution for FPGA logic, embedded and DSP designers delivers 2x faster run times and up to 38% faster performance
Xilinx, Inc. has introduced the delivery of its ISE Design Suite 10.1, a single unified release providing FPGA logic, embedded and DSP designers with immediate access to the company’s entire line of design tools with full interoperability. The ISE Design Suite 10.1 delivers significantly faster implementations with an average of 2X faster run times, allowing designers to complete more turns per day. Significant to today’s release is the introduction of SmartXplorer technology, developed specifically to address the top challenges of the design community – timing closure and productivity. SmartXplorer technology leverages distributed processing across multiple Linux machines to enable even more implementation runs per day, and up to 38 percent faster performance by leveraging distributed processing and multiple implementation strategies. SmartXplorer technology also provides tools that allow users to monitor each run with individual timing reports.
“The ISE Design Suite 10.1 has been invaluable for our design team, providing up to 80 percent run time improvement. Faster run times provide tremendous savings in development time, thus speeding our time-to-market,” said Yasuhiro Ooba, senior engineer in the Photonic Systems Group at Fujitsu, a leading provider of customer-focused information technology and communications solutions for the global marketplace
“SmartXplorer provides a powerful addition to our FPGA design flow. Without SmartXplorer we had to log onto multiple servers and manage individual PAR jobs manually,” said Honda Yang, logic designer at Xsigo Systems, Inc., the technology leader in data center I/O virtualization. “I was amazed to see the results of the different strategies. Using SmartXplorer, we achieved 20 percent faster performance.”
Ultimate Productivity with PlanAhead Lite & Strategy Based Implementation
With the availability of the PlanAhead Lite tool in ISE Foundation, users have access to a subset of the powerful floorplanning and analysis capabilities of the award winning PlanAhead design and analysis tool. Included at no additional cost, PlanAhead Lite features the revolutionary PinAhead technology, an intuitive solution designed to simplify the complexities of managing the interface between the target FPGA and PCB. PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout related changes that typically happen downstream by performing design rule checks during interactive pin placement. Once the pin assignments have been completed, PinAhead provides the ability to export I/O port information through either comma separated value (CSV) files or via VHDL or Verilog headers.
With ISE Design Suite10.1, Xilinx has also simplified the process of determining optimal implementation settings. Designers now have the ability to specify and set their own unique design goals, whether they are working to maximize performance, optimize device utilization, reduce dynamic power, or minimize implementation time. Designers using this area reduction strategy can realize an average of 10 percent better logic utilization.
Task Force Delivers Improved Verification
The ISE Design Suite 10.1 also benefits from the efforts of the company’s joint collaboration with Mentor Graphics, one of the industry’s leading EDA providers. Through the use of IEEE IP encrypted models, ISE Design Suite 10.1 offers up to 2X faster run times. The new performance optimized BRAM, DSP, and FIFO simulation models further reduce RTL simulation run times by an additional 2X.
Second Generation XPower Provides Improved Power Analysis and Optimization
Industry studies show meeting power budgets is a growing challenge for FPGA designers, especially as process geometries continue to shrink. The ISE Design Suite 10.1 provides capabilities for users to analyze power requirements early in the design and optimize dynamic power throughout the design process.
The second generation XPower power analysis tool enhances power estimation by providing an improved user interface to make it easy to analyze power by blocks, hierarchy, power rails and resources used. Information is presented in both text and HTML report formats. This is a significant advance from the static estimation web pages offered by other logic providers and a leap forward in providing accurate power dissipation information.
ISE Design Suite 10.1 provides power optimization that’s both convenient and extensive. Using the integrated ‘power optimization design goal’ feature, users have a simple, one-step process to specify power optimization. With improvements in the map and place & route algorithms, users can reduce dynamic power in their designs by an average of 10 percent for 65nm Virtex-5 devices and an average of 12 percent with Spartan-3 generation FPGAs.
Embedded & DSP Tool Integration
To help users achieve optimal embedded and DSP design results more quickly, ISE Design Suite 10.1 also introduces many ease-of-use enhancements to both the Xilinx embedded and DSP tools, including unified interoperability which allows users to easily add System Generator modules within the ISE Project Navigator. Inter-tool integration enhancements between EDK and System Generator for DSP technologies enable more sophisticated FPGA SoC design incorporating both embedded and signal processing.
EN-Genius Says…
Since a late embargo date will not permit coverage of Xilinx's latest branch of its V5 family until next week, I thought it would be a good time to take a quick look at the new toolset that will support it. Intended to streamline the design process for all their FPGA and PLD products, the ISE Design Suite 10.1 ties together the core logic design, embedded, DSP, and PCB-level integration tools released over the last year into a single easy-to-use package. Even if the package did not have so many performance-enhancing features, Xilinx would have done their customers an incredible favor simply by providing a single tool that enables FPGA newbies and occasional FPGA users to quickly produce useful, efficient designs without too much pain. When you add the fact that the same tool allows them to accurately understand the chip interactions with the PCB environment they run in, it's easy to get almost as excited about this package as Xilinx is.
Since Mathworks Matlab and Simulink seem to have become some of the most widely-used design tools for the rest of the industry, Xilinx was extremely smart to make their package compatible with them. This enables traditional logic developers and DSP programmers who may or may not be FPGA experts to fool with high-performance logic design and FPGA-based DSP using familiar tools. Having a single design environment from start to finish eliminates time-consuming, error-producing process of cutting, pasting and porting code between packages.
I won't bore you by re-stating all of the slick features crammed into DesignSuite 10.1 here, but I want to point out a couple that are especially intriguing. The Suite SmartXplorer is an exceptional productivity tool because it allows designers to parallel the time-consuming optimization process by using multiple workstations to run separate optimization scenarios. According to Xilinx, allowing you to try several different combinations of compiler switch settings at once can cut run time by around 50% while significantly increasing how much performance you can squeeze out of a particular FPGA.
It's also worth taking a moment to give a nod to the Suite PinAhead technology that handles many of the nasty little details involved with managing the interface between a FPGA and the PCB it sits on. By enabling intelligent pinout definition (either semi or fully automatic) and factoring PCB interaction into your model at the early stages of the design cycle, Xilinx both cuts the number of design spins you'll have to suffer through while significantly reducing overall design risk. Speaking of retiring design risk, Xilinx is also to be congratulated on having worked closely with Cadence, Mentor, and Synopsys to make timing verification around their hard IP cores shorter and easer.
Besides being available as a standalone software package, the ISE Design Suite is bundled with most of Xilinx's slick little development kits. Hopefully, I'll be able to convince Alex Mendelsohn, intrepid Editor of our toolsZONE, to take a closer look at one or more of these boards and give you an even better idea of how this new design suite actually works in real-world design scenarios.
The ISE Design Suite 10.1 consists of ISE Foundation, Embedded Development (EDK) with Platform Studio (XPS), System Generator for DSP, AccelDSP synthesis tool, ChipScope Pro analyzer and ChipScope Pro Serial I/O toolkit, PlanAhead design and analysis tool and ISE simulator. Users can install domain specific DSP, embedded and logic design products from either a DVD or electronic download. Using an electronic fulfillment process as the primary product delivery method provides users with access to not only the products they are entitled to, but evaluation versions of other Xilinx design tools.
All products in the ISE Design Suite 10.1 are immediately available with prices ranging from $495 to $2495. Full-featured 60-day evaluation versions can be downloaded from the Xilinx web site at no charge.
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