programmablelogicZONE Products for the week of May 5, 2008
Lattice Semiconductor Says…
Lattice And Aldec Form Alliance For FPGA Design And Design Verification
Active-HDL simulator delivers industry leading speed, and is the only OEM mixed language simulator for FPGA design
Lattice Semiconductor Corporation and Aldec, Incorporated announced a new OEM agreement that will deliver the only OEM FPGA mixed language simulator. Active-HDL Lattice Edition will be bundled with Lattice's ispLEVER design tool suite, providing mixed language simulation (VHDL, Verilog and SystemVerilog), co-simulation with Simulink from The MathWorks and simulation support for Lattice encrypted IP Cores.
"We’re excited to partner with Lattice and bundle our powerful mixed language simulator with Lattice’s FPGA solutions," said David Rinehart, vice president of marketing at Aldec. "Active-HDL Lattice Edition is derived from an industry-proven FPGA solution that offers the performance and functional capabilities that Lattice FPGA designers increasingly require to efficiently verify their designs."
Chris Fanning, corporate vice president, enterprise solutions, said, "Our alliance with Aldec enables Lattice to offer exceptional design verification capabilities that deliver incomparable value when bundled with our ispLEVER design tool suite. Our alliance with Aldec marks another milestone in Lattice’s commitment to deliver industry leading solutions to our FPGA customers."
About Active-HDL Lattice Edition
Active-HDL Lattice Edition boasts high performance simulation for Lattice designs, mixed HDL language support and a host of productivity enhancers ranging from testbench generation from a graphical waveform to co-simulation with The MathWorks Simulink. Active-HDL Lattice Web Edition is designed for single language simulation, either VHDL or Verilog, and smaller designs more typical of devices supported by the ispLEVER Starter and ispLEVER Classic tools.
About the Lattice ispLEVER Design Tool Suite
- Support for all Lattice CPLD/FPGA devices
- Mixed VHDL, Verilog, and SystemVerilog (Design) simulation support
- Testbench generation from waveforms
- Batch mode simulation
- Macro, Tcl/Tk and PERL script support
- Simulation of Lattice encrypted IP
- Code execution tracing
- Advanced breakpoint management
- Graphical waveform viewer and editor
- Memory viewer
- Simulink co-simulation (from within ispLEVER Design Tool Suite)
The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis, and more. The ispLEVER suite is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. ispLEVER Windows includes industry leading third party tools from Lattice partners Synplicity and Aldec for synthesis and simulation.
By adding support for mixed-language designs (VHDL and Verilog) and several other important features to its basic tool chain, Lattice has accomplished a nice upgrade to its development suite that helps level the playing field with its larger competitors. The excellent price/performance ratio of Lattice FPGAs and PLDs has made them a bargain for many applications but the more limited capabilities of their tool set has kept some designers from trying them out. While the Brand A and Brand X collections of development tools and IP libraries are still a bit richer, these important upgrades should make it attractive enough win over many new converts.
The upgrade includes the addition of Aldec ActiveHDL mixed-language-capable simulator described in the release along with a move to Synplify Pro, the premium version of the Synplicity Synplify synthesis and verification tool that has been their mainstay of their toolset for the last 10 years or so. Synplify Pro's mixed-language capabilities let designers use both Verilog and VHDL to define different elements within a single design. Besides making it easy to work in whichever language you feel most comfortable with, mixed-language synthesis lets you re-use any internally-developed or 3rd-party IP, regardless of what language it’s written in.
Synplify Pro also adds an automatic retiming feature that enables on-the-fly re-balancing of timing paths between registers – a handy function that can make timing closure much easier and faster in many applications. You now also get Synplicity HDL Analyst – a tool that produces an RTL block diagram from your HDL code listing. While hard-core designers can dream in HDL many folks find that a graphic representation of the logic they’re building is great tool for visualizing a whole design or working with a team that might not be familiar with the entire design.
Lattice has swapped out its earlier verification tool for Aldec Active-HDL, which supports mixed-language designs. The verification package also includes Aldec Memory Viewer that allows designers to see the state that a memory is initialized and what its state is in during any point during the simulation. This is a big step-up from the earlier package which only allowed you to see the memory inputs and outputs and guess at what was going on in the interim. You also get Aldec graphical waveform editor that generates simulated input waveforms for the simulator test bench suite. This replaces the generator you used to have to purchase at extra-cost from Mentor Graphics.
Besides bringing its synthesis and verification tool features and functions up to present industry standards, Lattice says it has made some under-the-hood improvements in memory efficiency that can significantly cut run times on larger designs. Other tweaks to the tools have improved their LUT/silicon use, allowing you to squeeze more functions on the same chip or, in some cases, dropping your existing design into a smaller, less costly device. It’s also nice to see that Lattice now offers its entire tool chain for both Linux and Unix as well as it original Windows version.
The increased flexibility and productivity that these improvements offer should help keep existing Lattice customers loyal while making it easier for potential customers to consider enjoying the cost advantages that many of their product lines have over equivalent devices from Brand A and Brand X.
Active-HDL Lattice Edition will be bundled with the next version of Lattice’s ispLEVER design tool suite. Active-HDL Lattice Web Edition will be made available free of charge to support the many users of Lattice’s ispLEVER Classic and ispLEVER Starter design tools. Lattice’s ispLEVER 7.1 for Windows, including Aldec Active-HDL Lattice Edition, will be available without charge for customers with active design tool maintenance contracts. The price of the full ispLEVER design tool suite starts at $895 for the Windows version.