|
 |
programmablelogicZONE Products for the week of May 19, 2008
Altera Corporation Says…
40-nm FPGAs and HardCopy ASICs
Stratix IV FPGAs and HardCopy IV ASICs Both offer SerDes transceiver options
Enabling designers to achieve new levels of integration and innovation, Altera Corporation has announced the industry’s first 40-nm FPGAs and HardCopy ASICs. The Stratix IV FPGAs and HardCopy IV ASICs, both with transceivers options, provide unprecedented densities, performance and low-power leadership. The Stratix IV family has up to 680K logic elements (LEs), 2X bigger than Altera’s Stratix III family, currently the largest FPGAs on the market. The HardCopy IV ASIC family offers equivalent densities as the Stratix IV devices and features up to 13.3 million gates. Altera 40-nm devices meet the diverse high-end application needs in a large number of markets such as wireless and wireline communications, military, broadcast and ASIC prototyping.
With the increasing demand for services such as video over Internet, high-speed wireless data and digital TV, designers need to deliver solutions that provide higher data rates, higher interface bandwidths, and increased data processing all in a power-efficient manner. To address these design challenges, Altera is leveraging its innovations in transceivers, memory interfaces, low-power technology and FPGA core architecture to offer new capabilities with its 40-nm devices.
Manufactured on TSMC’s 40-nm process, the Stratix IV FPGA family is comprised of two variants, an enhanced variant rich with memory and digital signal processing (DSP) resources (Stratix IV E FPGAs) and an enhanced variant with transceivers (Stratix IV GX FPGAs). Stratix IV GX FPGAs offer up to 48 transceivers operating at up to 8.5 Gbits/s, which provides designers with the industry’s highest available bandwidth, more than twice the bandwidth of any other FPGA. Stratix IV GX FPGAs also feature hard intellectual property (IP) support for PCI Express (PCIe) Gen 1 and 2 and also supports a wide range of protocols including, Serial RapidIO, XAUI (including DDR XAUI), CPRI (including 6G CPRI), CEI 6G, Interlaken and Ethernet.
To address the low-power demands of customers, the Stratix IV family members feature Altera’s patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design.
For the first time, Altera offers a transceiver-based ASIC option with the new HardCopy IV ASIC family. Using the Stratix FPGAs in design delivers the benefits of FPGA hardware and software co-design and co-verification—saving months in time to market—and the use of HardCopy ASICs delivers the benefits of ASICs in production.
“Today’s announcement significantly widens the density, performance and low-power advantages of the Stratix series versus competing offerings,” said John Daane, president, CEO and chairman of Altera Corporation. “Combined with the HardCopy ASIC family, Altera is the only company that can offer a complete high-performance solution that allows designers to quickly move from concept to volume production.”
The company also announced today enhancements to its Quartus II design software and delivered IP solutions optimized for 40-nm products. Quartus II software v.8.0 enables designers to achieve efficient team design and fast time to market through the highest performance, logic utilization and lowest compile times in the industry.
EN-Genius Says…
The direction of Altera’s ongoing slugfest with arch-rival Xilinx has just taken a left turn with the migration of their flagship FPGA series and its metal programmable ASIC platform to a 40-nm process. Driven by a fierce rivalry that makes Coke Vs. Pepsi look like a love-in, they're betting that they can overcome the potential technical issues that moving from their current 65 nm process to an aggressive 40nm technology might raise in order to gain a 2X density boost and a 50% power savings over a comparably-sized device. But while Xilinx will probably match or beat this new benchmark on their next go-around, they will have a tough time following Altera's strategy for streamlining the system they’ve put in place to help designers transition their products quickly and easily from FPGA-based implementations to lower-cost structured ASICs.
Both the Stratix IV family and its companion HardCopy structured ASICs are designed around TSMC’s 40-nm process which uses 193-nm immersion photolithography, strained silicon, and extremely low-k dielectric material. Altera says that they’ve plowed back the increase in operating speed the smaller transistors gave them into a lower power solution. Whereas the Stratix III had two speed grades, (a 1.1 V high-performance family and a 0.9 V low-power line that was 30% slower) the new Stratix IV is offered in a single 0.9 V version that delivers the same performance (up to 600 MHz clock speeds) as the earlier 1.1 V parts. You’ll enjoy even more dramatic power savings when you move your design from an FPGA to a HardCopy ASIC, which typically draws 50% less than an equivalent Stratix IV device.
As the release indicates, the Stratix IV family takes advantage of the higher densities that the 40-nm process offers by adding more logic elements (up to 680 k), signal processing elements (up to 1360 18 x 18 multipliers) and embedded memory blocks (up to 22.4 Mbit). The new platform uses the same DSP blocks used in Stratix III but offers a higher RAM-to-multiplier ratio (both in terms of total bits and total ports).
Besides providing more buffer, the additional RAM enables time-division multiplexing of DSP blocks by storing interim results and coefficients while another operation is in progress. Re-using a block’s available bandwidth enables a single DSP to do multiple functions rather than go to a larger chip. DSP element re-use is handled automatically by the new Altera DSP Builder tool which is included with their Quartus II Software v8.0 design tool package. When enabled, DSP Builder automatically re-uses DSP elements wherever possible as long as it can still meet the pre-defined performance constraints you’ve set. This allows designers to trade-off performance versus re-use on the fly within the Simulink environment.
The SerDes transceivers used in Stratix’s GX series have also been upgraded. The receiver linear equalizer has more taps and is augmented with a simple decision feedback equalizer on its front end. This, and an extra stage of pre-emphasis on the transmitter, boosts its maximum operating speed to 8.5 Gbit/s. Transceiver count has also been boosted from a maximum of 20 channels on Stratix III to 48 channels for the biggest Stratix IV chip. Hard logic cores enable support for up to four blocks of PCI Express (Gen 1 or Gen 2) in lane widths of 1x, 2x, 4x, or 8x. The same transceivers can be configured using soft cores to support XAUI, 8B/10B, GbE, or tri-speed SRIO at up to 3.125 Gbit/s.
Despite the substantial cost/density advantages Altera FPGAs will enjoy at this new process node, it seems that the long-term agenda of this jump is to get beyond simply competing with Brand X for the same FPGA sockets by opening up new markets for its HardCopy ASICs. Instead of their traditional approach of marketing HardCopy as a way to cost-reduce an FPGA-based design, Altera is trying to turn the tables and use its FPGAs to provide a faster, lower-cost, lower-risk ASIC development path than a regular foundry can offer. Earlier versions of the HardCopy program had most of the ingredients to make a highly-competitive chip development platform but there were several things it required before it could directly compete with classic ASICs and ASSPs executed in 65 nm and 90 nm.
Perhaps the most significant improvement that Altera engineers made to the HardCopy platform is to equip some of its family members with the robust multi-Gigabit SerDes transceivers found on their Stratix GX FPGAs. The same flexibility and performance that helped Altera FPGAs earn two of our Product of the Year Awards (see November 2005 and May 2007 reviews) should help make this new generation of HardCopy devices a great fit for any design involving PCIe, Serial RapidIO, XAUI, or other high-speed serial interconnects. Although the transceiver cores large size limits you to a maximum of 24 channels on a single chip, this should be more than enough for a vast majority of applications.
Altera has further smoothed the path between FPGA and ASIC by making a few improvements to the tool chain and cutting HardCopy up-front tooling costs. As always, you can use the same tool chain and VHDL/Verilog/Simulink files you used for your FPGA as the basis for your HardCopy ASIC. The new tool set features faster compile, analysis, and verification speeds (typically 20% - 50% faster) along with the new DSP Builder tool mentioned earlier. Once your design is working to your satisfaction on an FPGA, simply hand the file to Altera who handles all back-end timing closure and verification required to produce a HardCopy device.
HardCopy tooling costs have been reduced thanks to a multilayer mask technology that allows a set of two mask reticules to produce four different process steps. Eliminating one of the five photo masks previously required for the customization process is one of several tricks they’ve used to push the NRE for a typical chip down to around $400 k – far less than the million-odd dollars required to generate a mask set for a full-custom ASIC. This in turn reduces the number of chips required to hit the point where a HardCopy device unit cost drops below its FPGA equivalent. Altera says that, for most designs, this break-even point occurs between 5 k and 10 k units and that it can be even lower for high density designs. Lower-cost package options can drop the break-even point even further in applications where the device I/O is not being pushed to its full rated speed.
Regardless of how routine Altera makes the move to 40 nm sound, past history shows that being an early adopter of a cutting-edge process is a risky business. Although Xilinx early yield difficulties with the SerDes-equipped versions of its 90-nm Virtex 3 family are better-documented in the trade press, both companies have experienced their share of unexpected growing pains as they pushed their products to ever-smaller geometries. Altera hopes to avoid any surprises this time by running a series of nine test chips to verify performance and manufacturability across a widely-spaced set of corner-case processes before going to production.
When it comes to calculating a Vapor Index Rating for Stratix IV, the huge number of potential pitfalls for making such complex devices work in an aggressive and near-beta-stage 40-nm fab process is somewhat balanced by Altera’s relatively solid track record but some concerns still remain. I am also a little uncomfortable that they pre-announced these new devices by 6 months (or more) but suspect they were under some pressure in light of some of Xilinx recent releases or some other industry intelligence they have. In the end, I think Altera will be able to deliver the goods, but would not be surprised if they missed their schedule marks by 30 - 60 days.
Speaking of delivery, Altera politely declined to answer my question about whether we’d see their new value-priced SerDes-equipped Arria Family (see the May 2007 review) being produced in 40 nm any time soon. But, given the price pressures on these higher-volume parts, I would not be surprised to see 40-nm Arria devices beginning to ship within 6 months of the time that they have worked out any bugs they encounter when bringing Stratix IV into production.
Customers can start their StratixIV designs using Altera QuartusII design software v.8.0. Engineering samples of the first member of the StratixIV device family will be available in Q4 of 2008. Customer tape-outs for HardCopy IV ASICs will start in the Q3 of 2009.
Product Information StratixIV Devices
Product Information HardCopy IV ASIC Devices
Product Information HardCopy III Program
|
|
|
|
|
