Lattice Semiconductor Corporation has announced the availability of its third generation non-volatile FPGAs, the LatticeXP2 family. With enhanced capabilities, the LatticeXP2 family doubles maximum logic capacity to 40K Look-Up Tables (LUTs), improves performance 25% and adds dedicated DSP blocks, all while reducing the price per function by up to 50%. Power consumption has also been optimized on the 1.2-volt process technology, reducing static power usage by 33%. Designed using the industry's most advanced non-volatile FPGA technology, a 90nm embedded Flash process co-developed with Lattice's foundry partner Fujitsu, the LatticeXP2 devices provide the “instant-on” and reduced footprint benefits of earlier Lattice non-volatile devices, while also enhancing design security, RAM back-up and live update capabilities.
This latest product announcement comes over two years after the introduction of the previous generation 130nm LatticeXP family and demonstrates Lattice's ongoing commitment to leadership in the non-volatile FPGA segment. With over 20 years of experience in the non-volatile programmable logic arena, Lattice’s market experience has demonstrated repeatedly that as the premium charged for a non-volatile solution is reduced at each new process node, significantly more users will take advantage of the benefits of non-volatility.
“FPGA designers have enthusiastically accepted our prior generation, the LatticeXP Flash-based FPGA family, with thousands of cumulative design-ins worldwide to date,” said Stan Kopec, corporate vice president of marketing at Lattice Semiconductor. “We're gratified that this success has attracted the attention of one of our larger competitors who has recently attempted to jump on the non-volatile bandwagon, albeit with hybrid, multi-die devices that do not deliver the full advantages of our non-volatile FPGAs. The broad array of enhancements found in our new LatticeXP2 non-volatile FPGAs, reflecting our ‘More of the Best’ philosophy, is the result of our ongoing dialog with designers who have used our LatticeXP devices. With enhanced features and lower prices, LatticeXP2 devices will further expand the use of non-volatile FPGA technology and accelerate the growth of this increasingly important segment of the FPGA market."
The LatticeXP2 Family
The LatticeXP2 family consists of five members, with capacities from 5K to 40K 4-input Look Up Tables (LUTs). Embedded block memory provides up to 885Kbits in 18Kbit dual port blocks. For small scratch pad memories, LUTs can also be converted into small, distributed memory blocks. To support increasingly common DSP applications, up to 12 sysDSP blocks provide hardwired high-performance pipelined multiply and accumulate functions. The devices have up to four Phase Locked Loops (PLLs) that allow designers to align and synthesize clocks as required in their designs.
With power consumption such an increasing concern today for system designers, Lattice designed the LatticeXP2 family to use a 1.2-volt core voltage for low power consumption. In addition, the circuit design was tuned to reduce static power per logic function by approximately 33% overall. This means that while the largest device density has doubled to 40K LUTs compared to the 20K LUTs on the largest LatticeXP2 density, the static power consumed by the largest LatticeXP2 family member has increased by only 34%.
I/O capacities for the family range from 86 to 540 pins. Flexible I/O buffers support the most popular I/O standards, including LVCMOS, SSTL, HSTL and LVDS. These buffers are supported by pre-engineered I/O logic that simplifies the implementation of Double Data Rate (DDR) and source synchronous standards. This combination provides support for DDR2 memory interfaces at 400Mbps, high performance ADC/DACs at up to 750Mbps and 7:1 LVDS display interfaces at above 600Mbps. LatticeXP2 devices are available in a number of space saving Chip Scale Ball Grid Array (csBGA) packages, thin as well as standard Fine Pitch Ball Grid Array (ftBGA and fpBGA) packages and popular TQFP and PQFP options.
flexiFlash Architecture
Flash memory blocks are embedded within LatticeXP2 FPGAs to store the device configuration, providing a true single chip solution that Lattice calls the flexiFlash architecture. At power up or on user command, the data stored in the Flash memory is transferred into SRAM cells that control the configuration of the device. This transfer is done in a massively parallel fashion, enabling the device logic to be available in approximately 1mS, well ahead of the other devices in the system and much faster than SRAM-based FPGAs that use external boot PROMs, regardless of whether they are provisioned separately on-board or stacked in the same package. This instant-on capability is critical for many system functions such as power up sequencing, address decoding and reset logic.
By keeping the configuration bitstream on-chip, the LatticeXP2 devices are also inherently more secure than alternative multiple device or multi-chip module solutions. This security is enhanced by configuration read-back protection modes. A 64-bit erase/program lock protects against accidental or unauthorized device programming. A one time programmable (OTP) mode is provided for ultimate protection against unauthorized programming. Optional 128-bit AES encryption can be used to secure programming data being passed into the device.
The devices support up to 885Kbits of FlashBAK memory. This exclusive capability allows Embedded Block RAMs to be initialized at power up from Flash memory. During device operation, designers can also choose to write updated data from the block RAM back into the Flash memory. This provides a method to store data such as Power On Self Test (POST), microprocessor code and calibration data. An additional 0.6 to 3.3kbits of Flash memory is provided in the form of Serial TAG memory for general-purpose use by system designers for storage of device revision data, board identifiers and other data.
A Comprehensive Solution for Field Updates
Increasingly, electronic equipment is designed to support field updates and bug fixes. It is critical that these updates are done reliably, securely and, in many cases, without interrupting equipment operation. The LatticeXP2 devices address these three requirements. To protect against incomplete new configuration downloads due to communication or system failures during field updates, a “golden configuration” can be stored in an optional external SPI boot memory and the LatticeXP2 device can boot automatically from this configuration if bitstream errors are detected. An on chip, user defined 128-bit AES decryption key and associated circuitry allows programming data to be encrypted and securely sent to the device remotely, preventing program intercept and piracy. The devices also support TransFR (Transparent Field Reconfiguration) technology that allows new configurations to be loaded into the LatticeXP2 device while the I/O states are precisely controlled, allowing new configurations to be applied while the overall equipment continues to operate.
A New Generation of Design Tools
Concurrent with the announcement of the LatticeXP2 family, Lattice is also releasing a new generation of its ispLEVER design tool suite, ispLEVER version 7.0. In addition to providing design support for the LatticeXP2 family, the version 7.0 release provides major general enhancements including substantial speed and utilization improvements for all Lattice FPGA families, a greatly enhanced Power Calculator module, the entirely new Reveal design analysis tool with the industry's most advanced logic analysis triggering capabilities and many other enhancements. ispLEVER version 7.0 will be shipped by the end of June to all Lattice registered software users on maintenance contract.
EN-Genius Says…
Lattice’s higher-density, feature-encrusted upgrade of its LatticeXP family of budget FPGAs is another example of their recent efforts to push their trademark non-volatile (NV) technology into products designed to help it win large chunks of market share in the emerging high-volume applications that have begun to open up. They must be doing a good job since I’ve seen their aggressive and clever innovations driving the strategies of their larger competitors, such as Altera’s crash program to roll out its Arria family of lower-cost SerDes-equipped FPGAs to answer Lattice’s disruptively-priced ECP2M products. I also suspect that Xilinx introduced its own single-package 2-chip hybrid non-volatile version of its Spartan II FPGAs to try to compete with Lattice for the upper end of this growing market.
Although the move to 90 nm gives LatticeXP2 much higher logic densities for a given price/power point, there’s much more to the story. Since the release above provides such a coherent description of all the features that would entice you to jump ship from your current Brand A or Brand X device, I’ll try to keep the review focused on stuff that they don’t mention, or that particularly strikes my fancy. Most of these improvements are attributable to Lattice’s move to a 90-nm process, which they claim lets them price their new NV devices within 10% - 20% of parity for solution cost of equivalent SRAM-based FPGA products (when you include the boot Flash). They also make a good point in that most or all of that extra cost can be offset by using some of the XP user-accessible NV memory instead of a discrete Flash chip. And for those of you who need the instant-on capabilities and higher security (the code never leaves the chip) that a real embedded Flash technology provides, a hybrid NV FPGA co-packaged boot Flash may not even be a contender.
It’s worth noting that this is the first true NV FPGA to include significant amounts of hardwired DSP capabilities (see Fig. 1). They give you much more than the simple set of fast multipliers found in most other lower-end products by cramming in the same DSP block used in Lattice’s ECP2/ECP2M series. Including a set of hardware add, subtract and accumulate blocks in series with its parallel multiply elements gives you faster performance while saving your general-purpose logic elements for other purposes. This should come in very handy for implementing everything from FFTs and advanced filtering algorithms to direct up/downconverters. This makes them a good choice for cost-sensitive wireless infrastructure equipment as well as more exotic stuff like geo-seismic instruments, medical imaging equipment and all sorts of military gear used to help our warfighters reach out and touch someone. The shift to 90 nm gives you a nice speed boost, with a maximum stand-alone operating speed for basic logic blocks around 375 MHz, and DSP elements running at 325 MHz. Typical speeds for large designs is 200 - 225 MHz.
Meanwhile, their updated Flexi-Flash architecture keeps all the nifty old features, but adds user Flash capabilities plus some nice live update functions (explained in detail above) that make configuration management easier. This complements the enhanced security features that use integrated AES encryption to allow data to be moved in an encrypted state. A 64-bit Flash lock prevents unauthorized tampering but preserves programmability. For the truly paranoid, a one-time programmable mode completely disables the write mechanism voltage supply in a non-recoverable way to make the on-chip Flash the equivalent of a ROM. The new devices also allow their embedded block RAMs to be written back to the flash memory, enabling data generated by the chip (error codes, self-test results, processor code, serial #s etc…) to be preserved. You also get a so-called serial tag memory (size ranges from 0.6 to 3.4 kbit) accessable by both JTAG port and FPGA logic, which can be used for storing product data, serial number, date codes or calibration data.
You also get an enhanced toolset that lets you take advantage of the new features and make building FPGA-based SoCs (relatively) easy. The library of IP cores lets you embed anything from Ethernet MACs and DSP clocks to a 32-bit RISC processor and tie them together using an open-source Wishbone bus.
About the only real drawback I can find in these FPGAs is the fact that their emebedded Flash can tolerate fewer read/write cycles than an external boot Flash. For most applications, the 10 k+ cycles they’re currently willing to spec these parts for should be just fine, but products that require really frequent updates may have to get their FPGAs elsewhere -- at least for the moment. Lattice feels that the new series should be capable of many more cycles and is currently in the middle of verifying XP2 for 100 k cycles but the tests are still in progress.
The 17-k LUT LatticeXP2-17 is sampling in PQFP-208, ftBGA-256 and fpBGA-484. Lattice plans releasing the entire family during 2007. The LatticeXP2-17 will be priced at $12.00 in 100-k piece lots; other parts will cost as little as $5 and others at up to $25.
Data Sheet LatticeXFP2 FPGA
Data Sheet ispLEVER Design Tool Suite Version 7.0
