|
 |
programmablelogicZONE Products for the week of June 29, 2009
Altera Corporation Says…
Cyclone III LS FPGAs
Altera ships lowest power FPGAs with security features including anti-tamper, design-security and design-separation capabilities
Altera Corporation has announced a new low-power FPGA family with security features. The new Altera Cyclone III LS FPGAs offer the highest logic, memory, and DSP density per board area. These devices are the lowest power FPGAs at less than 0.25W of static power for 200K logic elements (LEs). The Cyclone III LS FPGAs, which are shipping now, target power and board-space-sensitive applications in all market segments including military and industrial.
The security features of the Cyclone III LS FPGA include a comprehensive information-assurance design suite that offers anti-tamper, design-security and design-separation capabilities. To protect highly sensitive information, the Cyclone III LS FPGAs' anti-tamper features include JTAG port protection, tamper monitoring, and cyclical redundancy check (CRC). Offering another layer of protection, these devices feature a proven industry-standard AES 256-bit encryption key for design security. Where size, weight, and power (SWaP) requirements are crucial, the design-separation feature of the Cyclone III LS FPGA enables high-assurance and industrial-safety applications in a single chip through logic, routing and I/O bank separation.
"The secret to the Cyclone series’ success has been a strong focus on customer applications, which allows Altera to supply the right mix of low power, high functionality, and small form-factor solutions," said Luanne Schirrmeister, senior director of component product marketing at Altera Corporation. "The introduction of the Cyclone III LS devices extends Altera’s low-power leadership and specifically addresses the security needs that are paramount for the military and industrial markets. We're offering a complete solution that protects against IP theft and tampering."
Cyclone III LS FPGAs allow a single-chip solution for next-generation military applications such as software-defined radio (SDR), crypto-subsystems, and crypto modernization equipment where long battery life, density at the lowest power, and small board space are required. The additional security features of the Cyclone III LS FPGAs give designers of secure communications applications the assurance that their information will be protected with anti-tamper technology.
The unique features of the Cyclone III LS FPGA also provide the optimal solution for industrial applications, specifically motion control, Industrial Ethernet, and industrial safety. Using the design-separation feature lowers system power and increases integration while offering design redundancy for safety-critical applications.
EN-Genius Says…
Boasting up to 200 k LEs and less than 0.25 W of static power Altera’s latest branch of its Cyclone III family (reviewed here March 2007) doubles down on their bet that FPGAs will play an increasingly important role in high-volume products. According to Altera, the LS family’s lower power consumption, high-levels of integration and new security features it offers are a direct response to their customer’s requests for FPGAs that can be used in applications where designers must watch power and cost with equal vigilance.
To achieve the reduction in power consumption Altera stuck with TSMC’s low-power 65-nm process (normally reserved for cell phones and handheld applications) used for the original Cyclone III series and made some relatively simple architectural tweaks that change the logic/DSP block/memory mix and trim the number of power-hungry I/O blocks. This helps clear up space for up to 8.2 Mbit of embedded memory and up to 396 embedded multipliers. By trimming the I/O elements to an appropriate level, the new family is able to give you up to 70% more logic, 2x more memory, and 80% more multipliers while holding the increase in power requirements to 30% - 40%.
Altera was able to offer further power savings by adding an option in their Quartus design suite that now allows you to optimize your design for power (with selectable timing margins) instead of speed. The result is still not as low-powered per unit of logic as, say, Actel’s IGLOO series (reviewed here October 2008) or Lattice’s ISPMACH CPLDs, but for the logic density and performance they offer, it is a significant achievement.
The Cyclone III LS’s design security and anti-tamper features are very appropriate for the rough-and-tumble world of OEM/ODM operations where many of the world’s consumer products are built and the IP that goes into them has been known to find its way into knock-off designs. The configuration data that’s passed between whatever external storage device (typically a small Flash memory) and the FPGA is protected using 256-bit AES encryption. For obvious reasons, the key is not stored on the unprotected Flash. At the time of manufacture, an encryption key is generated by a CORDIS tool function and blown into the FPGA’s separately battery-backed-up storage RAM via its JTAG port. After upload and testing, the JTAG port can be permanently disabled to prevent any further access to the key. These FPGAs also include anti-tamper circuitry that is supposed to automatically zero out the Flash memory if it detects any effort being made to get the key. This should prevent most casual attempts at messing with your IP although I’m not completely certain it’s enough to guard against a highly-motivated hacker. I’ve seen so many security flaws uncovered in so-called secure systems by the diligent efforts of the folks at Princeton’s Center for Information Policy that it’s tough to imagine that Altera’s security would be immune to such efforts.
I have fewer reservations about the design separation capability added to the Quartus II design software: a feature that generates fault-tolerant redundant logic designs that are instantiated as physically isolated partitions within the same device. By creating isolated blocks without any common electrical connection except at I/O and power, Altera’s software provides a cost-effective way to protect your design against SEUs and time dependent faults. Besides the obvious applications in military gear, I see this as an inexpensive way to add reliability to industrial, aerospace, and medical equipment or any other application where uptime is a priority.
This combination of reliability, security low power and low cost opens up lots of interesting applications for these FPGAs. The large number of embedded DSP blocks available in some models make it a great fit for software-defined radio (SDR) applications where it can be used to build signal chain elements from the decimation/filtering to source decoding on a single chip. Altera says that their DSP capability design separation features are already attracting significant interest for motor control systems: especially those requiring sophisticated PWM-based schemes. When I asked whether the Cyclone FPGAs were inexpensive enough to compete with low-cost signal controllers like TI’s Piccolo or Microchip’s dsPICs Altera explained that the hard silicon had the advantage for single-and dual-motor systems but that Cyclone offered significant cost savings in larger applications where the chip cost is spread across multiple motors.
Since the Cyclone III LS series is based on a mature architecture and a proven 65-nm fab process it’s a good bet that it will live up to the ambitious claims being made for it – and help Altera sell a lot of sand in the process.
Cyclone III LS devices are in production. All of the Cyclone III LS devices will be supported in the Quartus II software version 9.0 SP2.
Product Page
Quartus II Development Software
|
|
|
|
|
