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programmablelogicZONE Products for the week of August 3, 2009
Xilinx Says...
Virtex-6 FPGAs Enable Highest PCIe Bandwidth for Mainstream Applications with Compliant PCI Express 2.0 Endpoint
Second Generation PCIe FPGA Block Achieves PCI-SIG 1-8 Lane Compliance with 50% Lower Power and 15% Higher Performance than Previously Available
Xilinx has announced that its newest generation Virtex-6 FPGA family is compliant with the PCI Express 2.0 specification, delivering up to 50 percent lower power than previous generations and 15 percent higher performance than competitive offerings. The second-generation PCIe block integrated in Xilinx Virtex-6 FPGAs has passed PCI-SIG PCI Express version 2.0 compliance and interoperability testing for 1 to 8-lane configurations, adding to the broad range of design resources from Xilinx and its alliance members that support the widely adopted serial interconnect standard. This significant industry milestone is expected to accelerate mainstream development of high bandwidth PCIe 2.0 systems for communications, multimedia, server and mobile platforms, enabling applications such as high definition video, high-end medical imaging, and industrial instrumentation among others.
In addition, Xilinx has once again teamed up with key alliance members Northwest Logic Inc. and PLDA to provide Direct Memory Access (DMA) intellectual property (IP) cores for Virtex-6 FPGAs. This latest collaboration builds on their existing PCIe 2.0 soft IP for Virtex-5 FXT devices, the first FPGA to provide PCIe 2.0 x8-lane support with the Northwest Logic DMA core. DMA engines enable the efficient movement of data in systems, ensuring that the PCIe block in Virtex-6 FPGAs delivers maximum performance and bandwidth.
Designers can immediately begin the evaluation and design of PCI Express 2.0 compliant systems in Virtex-6 FPGAs. To assist in this effort, the Xilinx CORE Generator system delivered in the ISE Design Suite provides the PCIe core, reference design and all the scripts, basic testbench, and simulation models needed to streamline integration into customer designs. Designers can download at no charge the ISE WebPACK software or trial version of the full featured ISE Design Suite from Xilinx. http://www.xilinx.com/tools/webpack
“The demand for high-bandwidth connectivity is insatiable, and the PCIe 2.0 standard is critical to meeting the requirements of high performance, low power applications, especially in the telecommunications and server markets,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx. “Integrated PCIe FPGA blocks eliminate the I/O bottleneck in maximizing system performance, and were first introduced with our Virtex-5 FPGAs. Now with Virtex-6 FPGAs, designers in the pursuit of even higher bandwidth can take full advantage of our production-proven PCIe implementation with up to 50 percent lower power than the nearest competitive offering.”
Production-proven PCIe Support
Xilinx continues to lead the FPGA industry in support for PCI Express solutions. Xilinx was the first to integrate compliant PCIe version 1.1 blocks into programmable devices with its Virtex-5 FPGA family. PCIe 2.0 soft IP support soon followed for Virtex-5 FXT and Virtex-5 TXT devices, delivering the first FPGA-based solution to be compliant with the 5Gbps version of the standard. By leveraging all the application expertise and customer successes of its production-proven Virtex-5 FPGA PCIe solutions, Xilinx was able to achieve PCI-SIG compliance with Virtex-6 FPGAs for both PCIe 1.1 and 2.0 multi-lane configurations.
PCIe 2.0 blocks are integrated in all Virtex-6 devices with serial transceivers and are supported in all speed grades. These blocks include the complete transaction data link and physical layers, which use the Xilinx GTX transceiver technology and integrated BRAM.
The Virtex-6 FPGA Endpoint block for PCI Express also incorporates many easy-to-use features to simplify the design process, as well as configurations optimized for PCIe Endpoint and Root Port applications with additional resources to create a complete PCIe solution.
EN-Genius Says…
However noteworthy Xilinx’ announcement of PCIe SIG approval for its already-released Virtex6 FPGAs (see our February 2009 review) might be, it would not normally merit a review. But the fact that it was issued within a day of Altera’s near-identical news of its Arria II devices achieving PCIe compliance is a clear sign of the increasingly-intimate relationship between FPGAs and the PCIe ecosystem. Although Altera’s release pertains to its slower Arria II series*, the close timing between the two announcements is a good indicator of the intense rivalry for this rapidly-growing market: and the interesting products and tools that are likely to emerge from it. The fact that both companies’ press releases also highlight the availability of PCIe card-based development kits for their products only reinforces how many applications could benefit from the flexibility, low development costs and quick time to market that FPGA-based designs offer.
Xilinx’ ML605 development board is also certified as PCIe-compliant, giving developers a known-good Express Card form factor design to build their own designs on. Like its counterpart at Altera (announced July 27, 2009), the dev card includes an FPGA mezzanine card (FMC) interface. The FMC interface uses the FPGA’s spare SerDes transceivers to push data to and from the mezzanine card where a DSP, another FPGA, or other device, can support auxiliary processing functions. Having a generic base card that handles the system interface and other commonly-used functions enables quick development of application-specific modules that can be easily plugged into the base card. I’d expect to see versatile Express Card configuration used extensively in wireless applications and other compute-intensive environments which are driven as much by rapidly-changing standards and customer requirements as they are cost constraints.
Xilinx Virtex-6 LXT and SXT FPGAs are available now. The GTX serial transceivers in Virtex-6 LXT and SXT FPGAs are fully characterized across process, voltage and temperature (PVT), and the complete PCI-SIG compliance report is available. The Virtex-6 FPGA ML605 Evaluation Kit will be available in August 2009 and will be priced at $1995.
Data Sheet
* Although Altera’s announcement pertains to their lower-priced Arria II line whose 3.75 Gbit/s transceivers can only support PCIe Gen1 connections, their Stratix IV GX line, which competes directly with Virtex, achieved interoperability certification back in April 2009 (see Altera’s announcement).
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