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programmablelogicZONE Products for the week of August 25, 2008
Lattice Semiconductor Says…
Mixed-Signal Software Design Tool Supports Automotive Versions Of Power Manager II Devices
All power manager and Ispclock devices also supported
Lattice Semiconductor has announced the release of its PAC-Designer software design tool suite, version 4.99a. The tool suite now supports Lattice’s AECQ100-qualified automotive Power Manager II (LA-ispPAC-POWR1014/A) devices. The PAC-Designer tool suite also provides easy to use, point-and-click, intuitive design and verification support for all Power Manager and ispClock mixed signal devices.
“Today’s automotive designs use advanced CPUs, FPGAs and ASICs, which increases the number of board-mounted power supplies,” said Stan Kopec, Lattice corporate vice president of marketing. “Using Lattice’s PAC-Designer software tools, designers can quickly implement and fine tune the power management algorithm used to control and monitor these diverse power supplies. The resulting board-specific power management design is more accurate, requires less circuit board area and costs less than traditional designs using multiple off-the-shelf dedicated devices.”
The Benefits of PAC-Designer Software
Common power management functions found on circuit boards include hot-swap control, voltage supervision, supply sequencing and reset generation. To ensure board reliability, all board-mounted power supplies should be sequenced and monitored via a power management algorithm. Typically, the power management algorithm is either changed or fine tuned during the board debug process to meet unforeseen device power-up behavior. Traditional solutions are hard-wired and cannot be changed without an expensive board re-spin. Lattice’s Windows-based PAC-Designer software enables implementation of a new power management algorithm in Lattice’s Power Manager II devices within minutes.
Similarly, clock network designs require timing adjustments during the board debug phase. The Lattice ispClock devices support an in-system programmable skew mechanism. Using the PAC-Designer software, designers can precisely alter the clock skew of each of the clock nets. Traditionally, clock skew has been implemented by “snaking” clock traces on the board, and any change to the skew was implemented through a time consuming, expensive board re-spin. Using the PAC-Designer software, the clock network skew is altered simply by reprogramming the ispClock device.
EN-Genius Says…
These updates to Lattice PAC-Designer software tools should find a warm welcome both within the automotive electronics sector and many other markets where the unique programmable power management and clock distribution chips are cutting BOM costs, board space, and development time. The new package adds a couple of features specifically targeted for automotive applications but most are really intended to make analog design tasks easier for digitally-oriented engineers and take the headaches out of digital design for folks more comfortable with the voltage region that lies between the ones and zeroes. The improved tool also makes it easy to take advantage of the higher precision and new features available in the Lattice latest generation of chips.
One of the most noticeable additions to PAC-Designer is an optional command line interface which may be used instead of the normal GUI for programming/configuring the devices. I found the addition of an interface that went out of fashion over a decade ago to be rather curious but Lattice explained that they’ve found that the automotive electronics industry tends to be a bit conservative and that many engineers in the field are more comfortable with the simpler command line format. Also of note is a more efficient version of their so -called Fitter element that translates a design into the programming file using fewer hardware gates than the previous version.
The new PAC-Designer suite also takes full advantage of the higher levels of precision and functionality afforded by the second-generation LA-ispPAC-POWR1014/A power manager. In addition to the giving you more PLD gates, and analog monitor channels, the temperature-compensated bandgap reference source gives the parts 0.2% measurement accuracy – better than many discrete products I’ve seen! Using its differential monitoring mode ensures that you are guaranteed to be able to sense the difference in ground potential between the PLD and its sense point with 2% accuracy, or better, so that you can maintain tight voltage control across even larger boards with less-than-perfect ground plane schemes.
If that same circuit board is causing you problems with skew between clock signals, the programmable delays provided by Lattice ispClock PLD-based devices can take the pain out of clock distribution and generation (up to 400 MHz). Its programmable delays allow you to use software to make sure that all your clock edges line up instead of adjusting board traces.
Improving the design tool usability and gate efficiency adds to the growing list of reasons to consider going with Lattice PLD-based solutions for power and timing management in automotive electronics. In fact, the flexibility, wide temperature range, and high reliability that make these versatile chips so handy in cars should also make them a good choice in non-automotive applications like set top boxes, basestations, networking or medical equipment and industrial controllers.
The PAC-Designer software is available now and can be downloaded free of charge. High volume (over 150 k) pricing for the LA-ispPAC-POWR1014/A devices is $2.25. 10-k pricing for the ispClock 5610AV is $4.75.
Data Sheet LA-Power Manager
Data Sheet ispClock 5600A
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