programmablelogicZONE Products for the week of September 23, 2008
Xilinx Says…
Virtex-5 TXT Platform Delivers First Single FPGA Solution for Building 40G and 100G Telecommunications Equipment
Xilinx enables faster, low risk migration path to 100-Gigabit Ethernet telecommunications infrastructure for next era in multimedia delivery
Xilinx Inc. has announced the world’s first single-FPGA solution for telecommunications equipment manufacturers developing the next generation in Ethernet bridging and switching solutions. Aimed at spurring innovation and growth in the 40- and 100-Gigabit Ethernet (GbE) market, Xilinx has added the Virtex-5 TXT platform to its industry-leading, high-performance family of 65-nanometer (nm) field programmable gate arrays (FPGAs). The Virtex-5 TXT platform consists of two devices that deliver the highest number of 6.5Gbits/s serial transceivers available on any FPGA, and are fully supported with application-specific IP, development tools, and reference designs for implementing high-bandwidth protocol bridging.
“The explosive growth in Internet traffic for video over IP is creating the need to rapidly scale the world’s IP infrastructure. This has a direct impact on IP backbone network capacity, individual core router size, router-to-router link bandwidth, and the performance of optical transport networks used to carry traffic across wide area networks,” said Dean Westman, Vice President, Communications Business at Xilinx. “Virtex-5 TXT FPGAs tackle the challenges these requirements impose on hardware designers by enabling ultra-high bandwidth communications on a power-optimized programmable platform. This is a critical step forward for the telecommunications industry, and has the potential to accelerate development of the 40GbE and 100GbE infrastructure needed to deliver multimedia services.”
According to Communications Industry Researchers (CIR) analyst Lawrence Gasman, the industry efforts led by the IEEE to create 40- and 100-GbE systems will result in $4.3 billion in annual revenues by 2016, “Although the new Ethernet standards will impact every segment of the network from long-haul to interconnect, the initial demand thrust is expected to come from servers, which will account for just over 40 percent of the 40/100Gbits/s Ethernet market by 2016. Even with 40Gbits/s Ethernet, there will still be a need for 100Gbits/s, especially for switch connections, which will represent half of the 100GbE market in 2016.”
Flexible FPGA Architecture
The innovative ASMBL architecture first introduced with Virtex-4 FPGA family enables Xilinx to rapidly develop and deploy domain-optimized silicon platforms targeted at the technical requirements of specific markets and applications. With its forty-eight (48) 6.5Gbits/s GTX transceivers, the new Virtex-5 TXT platform is uniquely optimized for 100 Gigabit Ethernet applications. It is designed to improve signal integrity for reliable operation of 10/100Gbits/s links, lower power consumption per channel for better reliability, and provide programmable support for multiple protocols, thus easily adapted to evolving standards for the interface between 100Gbits/s optical modules and the media access controller (MAC).
Virtex-5 TXT devices offer the only single-chip solution with built-in flexibility and re-programmability to scale as 40GbE and 100GbE hardware requirements and standards mature, while delivering the 600Gbits/s total bandwidth required today to build network bridges such as:
- 100GbE to 120Gbits/s Interlaken
- 40Gbits/s Quad XAUI to 50Gbits/s Interlaken
- OC-768 to OTU-3
- SFI-5 to 4xSFI4.2
Non-Telecommunications Applications
The high-bandwidth capabilities of the Virtex-5 TXT platform are also well suited for high-performance computing and video broadcast applications. The high-transceiver count and ability to support multiple standards on a single programmable Virtex-5 TXT device delivers the flexibility, performance and low-risk required by these markets.
Leading-Edge Innovation
Early developers of 100GbE systems have relied on Virtex devices for their ability to deliver programmability and performance at the leading edge. In November of 2006, Xilinx FPGAs were used to showcase the world’s first successful 100GbE transmission through a live production network demonstrated at SC06 International Conference by Finisar, Level3 Communications, Internet2, and the University of California at Santa Cruz (UCSC). In June of this year, telecommunications services giant Comcast Corporation announced the successful completion of a 100GbE technology test over its existing backbone infrastructure between Philadelphia and McLean, VA using the industry’s first 100GbE router interface. The system used Sarance Technologies’ High Speed Ethernet IP Core (HSEC) running on a Virtex-5 FXT FPGA, which is now available as part of the new Virtex-5 TXT solution.
“The integration of our Ethernet IP solutions on a single Virtex-5 TXT FPGA is a compelling value proposition to enable telecom equipment manufacturers to get to market quickly,” said Farhad Shafai, Vice President of R&D, at Sarance Technologies. “Hardware developers can reduce their system costs by minimizing components and circuit board area, while also meeting power and thermal management targets. Not only does this ease the transition to 100GbE, it means that the wired telecom industry can maximize profits from the deployment of the next-generation multimedia infrastructure.”
EN-Genius Says…
The speed with which Xilinx turned out this specialized version of their Virtex 5 platform is both an indicator of how flexible their architecture is and how hot the potential market for high-bandwidth bridging is perceived to be. Unless the recent global economic calamities manage to completely the stifle rapid growth of Internet video content, Xilinx's new parts will be well-positioned to address the relentless demand for system bandwidth that’s a generation or two ahead of most commercial silicon.
Xilinx TXT family is a smart remix of elements from their existing Virtex 5 family to specifically address the need for protocol bridging, MAC functions, and other elements required to support 40 – 100 Gbit/s IP streams. To this end, Xilinx stripped out all the non-essential elements such as PowerPC cores, and DSP blocks usually found in its Virtex 5 parts, and ended up with several columns of programmable gates sandwiched in between two columns of its GTX 6.5 Gbit/s SerDes transceivers that are located on either side of the chip. Sitting behind each of the GTX transceivers is a programmable gearbox logic core that can be configured to support a wide variety of SerDes interface standards. The hard-coded logic can be set to support 8b/10b, 64/66 and 64/67 (Interlaken) line coding and MAC functions for 100G Ethernet MAC, 50G/120G Interlaken connections. Other MAC logic or line coding schemes can be implemented using some of the TXT ample FPGA logic. For more details on the GTX transceivers, see my April 2008 review of Xilinx FXT series.
 The two columns of 5 – 6 Gbit/s transceivers on each side can be ganged together in pairs to support a RXAUI connection to a 10GbE PHY, or combined to form a single 100 Gbit/s connection. The logic in between the interfaces can be used to implement nearly any bridging or packet processing function required to tie system elements together.
Some of the other real-world applications already in progress by Xilinx customers include 100G Line Cards, 100GigE MAC to Interlaken bridges, 40G Line Cards, and OC-768 to OTU-3 bridges. Power varies by application but a worst-case analysis (per NEBS requirements) for a 100GbE MAC to Interlaken function with some packet processing in the middle will consume around 20 W.
The TXT series makes good use of the Virtex 5 existing design tools and IP libraries. The new devices are fully supported by Xilinx ISE Design Tool Suite, as well as both the PlanAhead design optimization and ChipScope Pro Serial I/O tools. Models and other support are also available from Synopsys, Mentor ELDO, Ansoft Nexxim, and Agilent ADS. There’s already a good selection of 100G IP available including a 100G Ethernet to 120G/50G Interlaken bridge from Sarance, SFI-5, OC-768, OTU3, EFEC, and GFEC cores from Avalon Systems, and a RXAUI core from MorethanIP.
 Since nearly all of the TXT family technology is already proven on existing Virtex 5 products, it earns a relatively low Saltshaker Rating. I still have a few a few lingering doubts about the ability of Xilinx's 6-Gbit/s GTX transceivers to perform in challenging conditions such as backplanes where high levels of crosstalk, reflections and attenuation may seriously challenge the transceiver equalization capabilities (See my April 2008 review for details) but it’s much less of a factor in these applications which do not usually involve box-to-box or backplane connections. I expect them to encounter few, if any, problems when driving the shorter, single-board, chip-to-chip connections that most of these devices will encounter when performing bridging functions.
Xilinx TXT should do a nice job of providing protocol bridging, MAC functions, and other IP video support during the 18 – 24 months I expect it will take for the first 100 Gbit/s-capable ASICs and merchant silicon to become available. Xilinx is more pessimistic about the industry’s ability to step up to 100 Gbit/s, and thinks that the technology’s high complexity, its still-undefined standards, and high entry costs may push out merchant and ASIC solutions even further. They also say that their long experience with helping designers migrate their designs from 1GbE to 10GbE leads them to expect that they’ll retain lots of business even when merchant silicon catches up because of the flexibility it offers.
Customers can immediately begin designing with Virtex-5 TXT FPGA devices using the available ISE design suite service pack 3. The Virtex-5 TX150T and Virtex-5 TX240T devices will begin sampling by the end of calendar 2008 with production devices available in Q1 of 2009. The TX150T device will list for under $500 in 5000 piece lots.
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