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programmablelogicZONE Products for the week of December 10, 2007
Altera Corporation Says…
MAX IIZ CPLDs Cut Power, Cost, and Enhance I/O in Portable Applications
Expanding its low-power portfolio of programmable logic solutions, Altera Corporation has announced the new, zero-power MAX IIZ CPLD designed specifically to address the power, package and price constraints of the portable applications market. Offering a resource advantage of up to six times the density and three times the I/Os compared to competing traditional macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements at the same or lower power while saving board space.
Adding zero-power and ultra-small packages to the most popular CPLD series in the industry, the MAX IIZ devices deliver the many benefits of CPLDs—including flexibility, faster time to market, and board-level integration—to handsets and other portable applications. “The introduction of MAX IIZ devices is an exciting extension of Altera’s power conscious product portfolio,” said Luanne Schirrmeister, director of marketing, low-cost products at Altera. “From smart phones to portable media players, designers of today’s portable applications need the ability to differentiate their products for market success, without increasing power or form factor. As a result, we optimized MAX IIZ devices to offer the best combination of zero power, small package,and low cost.”
Features and Benefits of MAX IIZ CPLDs
MAX IIZ devices are available in densities of 240 and 570 logic elements (LEs). The devices are available in ultra-small MBGA packages with up to 160 I/Os. This increased logic density and greater I/O count allow greater integration of existing functions from other devices, substantially reducing board space and power consumption while lowering overall system costs.
MAX IIZ devices break through the power, space and cost limitations of traditional macrocell-based CPLDs by combining non-volatility and instant-on performance with an innovative look-up table (LUT) logic structure. The devices utilize a 0.18-micron process, 1.8V core voltage and 6-metal-layer flash to provide both high functionality and zero-power consumption in a single device. The advanced system features of MAX IIZ CPLDs , such as user flash memory, an internal oscillator, cost optimization, greater density, smaller packages and lower power consumption, far surpass those of all traditional macrocell-based CPLDs.
Altera Low-Power Portfolio
Altera offers a complete line of low-power solutions. With industry-leading low power performance in the Altera Stratix III and Cyclone III FPGAs, HardCopy structured ASICs and MAX IIZ CPLDs, Altera’s devices are used in a wide range of power-conscious applications, such as high-performance computing, military radios, mobile phones and digital consumer products.
Software Support
MAX IIZ devices are supported by free Quartus II Web Edition software version 7.2, SP1. With this new version of the easy-to-use Quartus II software, Altera delivers the lowest development cost and fastest time to design completion to ensure a smooth and successful design flow. The Quartus II software also integrates seamlessly with all leading third-party synthesis and simulation tools. Customers can download the subscription edition and web edition of the Quartus II software at www.altera.com/download.
EN-Genius Says…
It’s hard to imagine anything as humble as a PLD being exciting, but Altera’s MAX IIZ series comes pretty close because of the much higher logic (up to 570 LEs) and I/O density (up to 160 I/Os) it brings to low-cost, high-volume designs. Altera emphasizes how the device low power (8.9 mA @50 MHz, 29 µA static) and small footprint (5 mm2 MBGA) make it a natural choice in portable consumer electronics but the higher logic density opens up possibilities for lots of other markets as well.
This re-spin of Altera’s venerable MAX series trims power using several techniques including a re-design of the power management block’s low-voltage power-on reset circuits. MAX II’s on-chip bandgap reference source and comparator draw a bit less power than earlier incarnations, and users now have the option of disabling it altogether after power-up. Cutting out the bandgap circuit allows designs that can support their own post-power-up low-voltage reset functions and can save around 2 mA worth of operating current.
The IIZ series saves more power by using transistors with slightly higher logic voltage thresholds which significantly reduces their leakage current. While they run a little slower than a standard product, (maximum clock rate is still TBD but early characterization indicates a preliminary minimum end-to-end propagation delay of 6 - 7 ns) Altera is confident that it should be more than fast enough for nearly all the glue logic applications they’ve traditionally been used in, as well as the more sophisticated functions that the higher logic density will enable.
In embedded applications, the extra logic can often pay for the entire PLD by providing extra serial or parallel I/O for low-cost, bare-bones microcontrollers. It can also offload timers, masking functions, or even simple state machines that save precious processor cycles and milliamps. The MAX family ability to run its I/O banks at different voltages makes it easy to run legacy components with higher logic level voltages (up to 5 V) without the need for an external level shifter. That may be enough to justify the CPLD’s cost alone. MAX IIZ has done so much to narrow the gap between merchant silicon and programmable logic at the low end of the food chain that I really do believe Altera’s ambitious clams that their devices are more cost-and power-effective than standard logic in many portable/handheld applications.
Production-qualified MAX IIZ EPM240Z M68 devices will ship in Q1 of 2008 at $1.25 in high volumes. All MAX IIZ devices will be shipping by Q2 of 2008.
Data Sheet
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