programmablelogicZONE Products for the week of November 13, 2006
Altera Corporation Says…
Stratix III FPGA Family Uses Efficient Architecture And Programmable Power TechnologyTo Deliver 25% Speed Boost, 50% Less Power
Altera Corporation announced its Stratix III FPGA family, delivering the industry’s lowest power consumption of any high-density, high-performance programmable logic device. Built on TSMC’s 65‑nm process, Stratix III FPGAs feature groundbreaking innovations including hardware architecture advancements and Quartus II software enhancements. Working together, these new features deliver 50 percent lower power, 25 percent higher performance and 2x the density compared to previous generation Stratix II devices.
Altera Stratix III FPGAs feature two new technologies that dramatically lower power while meeting high-performance requirements. Reduced power consumption is achieved by utilizing Altera’s innovative Programmable Power Technology, which maximizes performance where needed while delivering the lowest power elsewhere in the design. Programmable Power Technology enables every programmable logic array block (LAB), DSP block and memory block to independently operate at high-speed or low-power mode. The PowerPlay feature in Quartus II software version 6.1 automatically analyzes the design and identifies which blocks are in the critical path and demand the highest performance, setting these to high-speed mode. All other logic is automatically put into low-power mode. The second power-optimizing feature, Selectable Core Voltage, provides the designer options to select either 1.1V for designs needing the highest performance or 0.9V for designs requiring minimum power consumption.
“The OneBase family of Base Station Systems offers network operators a range of techniques and deployment technologies to meet build-out requirements and deliver coverage, capacity and high-quality service to end-users,” said Bob Suffern, vice president, research and development at Andrew Corporation. “The Stratix and HardCopy families have been a key enabler of Andrew’s success in this space. And Stratix III, with its lower power consumption, higher integration and path to HardCopy III structured ASICs remains at the heart of our design plans.”
Stratix III devices offer the highest memory-to-logic ratio and DSP performance compared to any other FPGAs in the industry. To address a full range of high-end applications, three new Stratix III family variants are offered: one delivering balanced logic, memory and DSP resources for general-purpose applications, a second providing enhanced memory and DSP resources for memory- and DSP-intensive applications and a third offering integrated transceivers for high-bandwidth interface applications. Additionally, Altera provides a unique and risk- free migration path from Stratix III FPGAs to HardCopy structured ASICs.
“As high-end FPGAs are increasingly used as the heart of many electronics systems, it is critical for OEMs to achieve new levels of performance and density while minimizing power consumption,” said Jordan Plofsky, Altera’s senior vice president of marketing. “Stratix III FPGAs feature a perfect combination of hardware enhancements and new software capabilities designed to maximize productivity. Our customers can now design their next-generation systems with confidence and successfully get to market quickly and efficiently.”
Stratix III Features
The Stratix III family architecture is based on the same FPGA fabric as the industry-leading Stratix II family featuring high-performance adaptive logic modules (ALMs). Working together, Stratix III FPGAs and Quartus II software offer the industry’s most innovative design methodology for improved productivity and performance. This enables designers to efficiently move their designs from development to production and meet both technical and business goals. Stratix III features include:
- Programmable Power Technology: Enables every programmable logic array block (LAB), DSP block and memory block to independently operate at high-speed or low-power mode. The PowerPlay feature in Quartus II software automatically controls the mode of each block based on performance requirements.
- Selectable Core Voltage: Enables designers to choose 1.1 V core voltage for high-performance applications or 0.9 V core voltage for the lowest power consumption.
- Highest Performance: Stratix III devices are 25 percent faster than the prior generation and, at a minimum, provide a full speed grade advantage over any competing FPGA family.
- Highest Density: Stratix III FPGAs bring a 2x density advantage over prior generation FPGAs and are the highest-density FPGAs in the industry.
- Flexible I/O: Supporting over 40 I/O interface standards, Stratix III I/Os deliver industry-leading performance, flexibility and signal integrity.
- External memory interfaces: Industry-leading memory interface performance with programmable I/O delay, programmable drive strength and slew rate, read/write leveling and 31 embedded registers per I/O for maximum DDR3 performance are new to Stratix III FPGAs.
- Superior signal integrity: Stratix III FPGAs utilize increased power/ground to user I/O ratio, optimized signal return paths, adjustable slew rate control, staggered output delays and calibrated on-chip termination for best-in-class signal integrity.
- Highest-performance DSP capability: Stratix III FPGAs deliver up to 300 times more multiplier/accumulator performance than the highest-performance digital signal processors, while providing lower power, smaller board footprint and lower overall system costs for equivalent performance.
- TriMatrix memory: Stratix III TriMatrix memory includes three sizes of memory blocks, MLAB blocks, M9K blocks and M144K blocks, that enable higher memory bandwidth than any other FPGA memory architecture and up to 17 Mbits of memory performing at 600 MHz.
- Design security: Stratix III devices are the only FPGAs with support for 256-bit Advanced Encryption Standard (AES) volatile and non‑volatile security key to protect designs from copying, reverse engineering and tampering. This feature brings ease-of-use and industry-leading IP protection.
- Quartus II PowerPlay software: PowerPlay optimization and analysis technology automatically analyzes designs and optimizes them for the lowest power while meeting users design constraints. No other power optimization software is as easy to use or effective in minimizing power.
- Quartus II software v6.1 advanced design features: Quartus II software version 6.1 enables the highest levels of productivity and the fastest path to design completion for high-density FPGA designs with the TimeQuest timing analyzer, top-down and bottom-up incremental compilation and multiprocessor support.
Third-Party Support for Stratix III FPGAs
In addition to the Quartus II design software, tools from leading EDA vendors Aldec, Inc. (System Verification Environment (SVE)), Magma Design Automation Inc. (Blast FPGA), Mentor Graphics Corporation (Precision Synthesis) and Synplicity, Inc. (Synplify Pro FPGA synthesis and Synplify DSP software) all support the Stratix III device family, ensuring the highest quality of results in Altera devices.
EN-Genius Network Says…
Even a quick glance at Altera’s new Stratix III FPGAs reveals a number of architectural and transistor-level features that reflect the rapid evolution their flagship product family has undergone to meet the tough realities they face as programmable logic moves from the edge to the center of many design cycles. Their three application-specific series (plus a structured ASIC line that’s in the works) all reflect the lengths to which Altera has gone to meet their customers needs for lower power, faster speeds, improved I/O capabilities, and higher logic densities. But moving to a 65-nm process is only part of the reason these once power-hungry beasties are now nearly as power-efficient as some ASICs, and damned near as fast as well.
The new architecture crafted for 65-nm processes doubles cell density and halves per-gate power consumption. A good chunk of the performance jump can be chalked up to a combination of improved low-k dielectrics in the transistors, and the use of smaller, faster strained-gate transistors. But Altera also borrowed a page from their competitor, Xilinx V4 series (reviewed here June 2004), and adopted a triple oxide process to produce three families of transistors, each with their own distinctive thresholds and speeds. This allows them to use a thicker oxide to build devices that have sufficiently high operating voltages for I/O connections and build the remainder of FPGA from a mix of standard transistors and devices that are faster, albeit leakier. The faster devices are strategically dotted in as needed in time-critical paths such as carry chains.
Although I could not confirm it, well-placed sources say they’re probably using the same range of oxide thicknesses (around 1 nm) for their 65-nm triple oxide products as they used in their dual-oxide 90-nm products. With 2+ years of production experience behind it, this part of the fab process should be relatively mature, something that should keep yields up despite the extra manufacturing steps involved. Altera has also guarded against some of the inevitable yield problems that crop up on a high-density 65-nm design by adding redundant resource blocks which can be swapped in as needed. Altera says that the big trick here was finding a way to keep the timing characteristics of both primary and backup blocks as closely matched as possible. My confidence in Altera’s ability to produce 65-nm products was further raised when I heard that they have been involved with basic research on moving to 65-nm since mid-2003 -- and even done several test runs using 45-nm geometries.
The Stratix III series also boasts a unique selectable threshold feature that allows you to select (at time of programming) whether the device’s logic level runs at a power-saving 0.9 V or a speedier 1.1 V. Altera was mum about the details but, if it works as advertised, it should provide designers with the moral equivalent of the power/economy button found on many automatic transmissions.
Besides these transistor-level improvements, Altera has made some very smart architectural changes that squeeze even more watts out of their design while giving you more performance and more efficient gate use. The basic structure of Stratix III products is based on a logic block, a group of around 10 LUTs that can be programmed to function as either high-speed or low-power logic to match the demands of the function it’s assigned (see Fig. 1). Furthermore, any unused logic blocks are held at a standby level that burns even less static power. This enables only the blocks that really need to run at full speed (usually 15% - 25% of a typical design) to actually run in the high-power mode. I’m told that the logic required to implement this adds only a few percent to the chip’s silicon overhead, a trade-off that appears to be well worth the real estate.
We ran out of time during my briefing before we could dig deeply into the Quartus II design software but it’s apparent that new more accurate tools will be needed to handle the faster, more complex, designs that Stratix III enables. From the quick overview I got, it looks like the timing engine, power optimizer and place & route engine that work within Quartus II environment should be up to the task but I’d welcome insights from readers who are actually familiar with Altera design tools.
Altera has taken a very aggressive approach in its first 65-nm products by implementing several new technologies that could yield them significant advantages in terms of power, performance, and usability. They seem to have balanced these potentially-risky moves with some very prudent design techniques and extensive design verification. This, and Altera’s good history of actually being able to produce the devices they announce, gives them a surprisingly low Vapor Index Rating for such an ambitious product launch. It will be interesting to see whether the SerDes transceivers in this new family match, or beat the excellent performance of their 90-nm devices and how they stack up against Xilinx’s recently-announced Virtex 5 65-nm products (reviewed here October 2006).
The other thing I’ll be watching closely is how quickly much of this new technology will trickle down to Altera’s lower-priced FPGA lines. While there will always be a brisk trade in $500+ FPGAs as time-to-market accelerators and alternatives to ASICs in high-end equipment, I think that the changing economics of programmable logic will produce the greatest market growth in the low end, where $5 - $25 devices are displacing merchant and custom silicon in high-volume applications. If this is true, Altera’s long-term success lies in how quickly it can apply some of the important lessons learned in developing the Stratix III series to its Cyclone product line, and even its MAX CPLD devices.
Engineering samples of the first Stratix III device will be available in Q3 of 2007. Stratix III designs can be started today using the Quartus II design software v6.1. Pricing will start at $549 for 1000-piece lots.
|
